TSV constraints related to temperature excursion, pressure during molding, materials used and handling loads

Microsystem Technologies

Volumn 15, Issue 1 SPEC. ISS., 2009, Pages 181-190

  Fałat, Tomasz ^a   Friedel, Kazimierz ^a   Marenco, Norman ^b   Warnat, Stephan ^b  

^a WROCLAW UNIVERSITY OF TECHNOLOGY   (Poland)

^b FRAUNHOFER INSTITUTE FOR SILICON TECHNOLOGY ISIT   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CHIP SCALE PACKAGES; ELECTRONIC EQUIPMENT MANUFACTURE; FLIP CHIP DEVICES; FORMING; MATERIALS HANDLING; MOLDING; SEMICONDUCTING SILICON COMPOUNDS; SILICON; SILICON WAFERS; STRESSES; WAFER BONDING;

DECOUPLING; FEM ANALYSES; MANUFACTURING; MECHANICAL ASPECTS; MECHANICAL STRESSES; MEMS DEVICES; ON WAFERS; SILICON VIAS; SUBSTRATE WAFERS; TEMPERATURE EXCURSIONS; WAFERLEVEL PACKAGING;

ELECTRONICS PACKAGING;

EID: 54049120009     PISSN: 09467076     EISSN: None     Source Type: Journal    
DOI: 10.1007/s00542-008-0648-6     Document Type: Conference Paper

References (5)

1. Coletti G et al (2005) Mechanical strength of silicon wafers and its modeling. In: Proceedings of 15th workshop on crystalline silicon solar cells and modules, Vail Colorado, USA, 7-10 August 2005
2. Coletti G et al (2006) Mechanical strength of silicon wafers depending on wafer thickness and surface treatment. In: Proceedings of 21st European photovoltaic solar energy conference and exhibition, Dresden, Germany, 4-8 September 2006
3. Pecht M et al (1999) Electronic packaging, materials and their properties. CRC Press, Washington
4. Steinzig M (2000) Bend tests of silicon ladders to determine ultimate strength. HYTEC Incorporated report HTN-102050-0016, 08/03/2000
5. F Yu 2002 Stress analysis in silicon die under different types of mechanical loading by finite element method (FEM) IEEE Trans Adv Packag 25 4 522 527 10.1109/TADVP.2002.807561