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Volumn , Issue , 2009, Pages 972-979

Design, processing and reliability characterizations of a 3D-WLCSP packaged component

Author keywords

[No Author keywords available]

Indexed keywords

AIR-TO-AIR THERMAL CYCLING; COST EFFECTIVE; DESIGN CONSIDERATIONS; LEAD-FREE; LOWER COST; MANUFACTURING PROCESS; MARKET DEMAND; PACKAGE DENSITY; PACKAGE STRUCTURE; PACKAGING DENSITY; PACKAGING SOLUTIONS; PROCESSING TECHNOLOGIES; RELIABILITY CHARACTERIZATION; RELIABILITY PERFORMANCE; SECOND LEVEL; SMALL PACKAGE; STAND-OFF; TEST VEHICLE; THREE-DIMENSIONAL (3D) PACKAGING; TIME TO MARKET; UNDERFILLS; WAFER BUMPING; WAFER INTEGRATION TECHNOLOGY; WAFER LEVEL; WAFER LEVEL CSP; WAFER THINNING;

EID: 70349680427     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2009.5074131     Document Type: Conference Paper
Times cited : (13)

References (12)
  • 1
    • 65349177340 scopus 로고    scopus 로고
    • Packaging and Assembly of 3-D Silicon Stacked Module for Image Sensor Application
    • Yoon, S. W., Ganesh, V. P., et al, "Packaging and Assembly of 3-D Silicon Stacked Module for Image Sensor Application, " IEEE Transactions on Advanced Packaging, Vol. 31, No. 3 (2008), pp. 519-526.
    • (2008) IEEE Transactions on Advanced Packaging , vol.31 , Issue.3 , pp. 519-526
    • Yoon, S.W.1    Ganesh, V.P.2
  • 3
    • 33748533457 scopus 로고    scopus 로고
    • Three-dimensional integrated circuits
    • July/September
    • Topol, A. W., et al. "Three-dimensional integrated circuits, " IBM Journal of Research and Development. Vol. 50, No. 4/5, July/September, 2006, pp. 491-506.
    • (2006) IBM Journal of Research and Development , vol.50 , Issue.4-5 , pp. 491-506
    • Topol, A.W.1
  • 5
    • 51349083790 scopus 로고    scopus 로고
    • Chip scale, flip chip and advanced chip packaging technologies
    • C. A. Harper, ed. McGraw-Hill, (New York
    • Baldwin, D. F., and Higgins, L. "Chip Scale, Flip Chip and Advanced Chip Packaging Technologies, " Electronics Packaging & Interconnection Handbook, C. A. Harper, ed., McGraw-Hill, (New York, 2004), pp 873-885.
    • (2004) Electronics Packaging & Interconnection Handbook , pp. 873-885
    • Baldwin, D.F.1    Higgins, L.2
  • 10
    • 50049124751 scopus 로고    scopus 로고
    • Process Development of Void Free Underfilling for Flip-chip-on-board
    • Singapore, December
    • Ying, M., Tengh, A., et al, "Process Development of Void Free Underfilling for Flip-chip-on-board, " 9th Electronics Packaging Technology Conference, Singapore, December, 2007.
    • (2007) 9th Electronics Packaging Technology Conference
    • Ying, M.1    Tengh, A.2
  • 12
    • 0242355161 scopus 로고    scopus 로고
    • No-Flow underfill process modeling and analysis for low cost and high throughput flip chip assembly
    • Kim, C. and Baldwin, D. F., "No-Flow Underfill Process Modeling and Analysis for Low Cost and High Throughput Flip Chip Assembly, " IEEE Transactions on Electronics Packaging Manufacturing, Vol. 26, No. 2 (2003), pp. 156-165.
    • (2003) IEEE Transactions on Electronics Packaging Manufacturing , vol.26 , Issue.2 , pp. 156-165
    • Kim, C.1    Baldwin, D.F.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.