Reliable design of electroplated copper through silicon vias

ASME International Mechanical Engineering Congress and Exposition, Proceedings (IMECE)

Volumn 4, Issue , 2010, Pages 497-506

  Liu, Xi ^a   Chen, Qiao ^b   Sundaram, Venkatesh ^c   Muthukumar, Sriram ^d   Tummala, Rao R ^b,c   Sitaraman, Suresh K ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b Georgia Institute of Technology   (United States)

^c GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^d INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; DEFECTS; ELECTRONICS PACKAGING; FINITE ELEMENT METHOD; INTEGRATED CIRCUIT INTERCONNECTS; LOW-K DIELECTRIC; SILICA; SILICON; SILICON OXIDES; STRESSES; TEMPERATURE; THERMAL EXPANSION; THREE DIMENSIONAL INTEGRATED CIRCUITS;

3-D SYSTEM INTEGRATION; COEFFICIENT-OF-THERMAL EXPANSION; CU PUMPING; ELECTROPLATED COPPER; ENABLING TECHNOLOGIES; HIGHEST TEMPERATURE; LOWS-TEMPERATURES; THERMAL EXPANSION MISMATCH; THERMOMECHANICAL RELIABILITY; THROUGH SILICON VIAS;

RELIABILITY;

EID: 84881462684     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1115/IMECE2010-39283     Document Type: Conference Paper

References (14)

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