A cyclic vernier TDC for ADPLLs synthesized from a standard cell library

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 58, Issue 7, 2011, Pages 1511-1517

  Park, Youngmin ^a   Wentzloff, David D ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

All digital PLL (ADPLL); standard cell library; synthesis; time to digital converter (TDC); Vernier

Indexed keywords

DIGITAL LIBRARIES; PHASE LOCKED LOOPS; SIGNAL PROCESSING; SYNTHESIS (CHEMICAL);

ALL DIGITAL PHASE LOCKED LOOP; ALL-DIGITAL PLL; AUTOMATIC DESIGN TOOLS; DIGITALLY CONTROLLED OSCILLATORS; PROCESS TECHNOLOGIES; STANDARD CELL; TIME TO DIGITAL CONVERTERS; VERNIER;

FREQUENCY CONVERTERS;

EID: 79959775626     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2011.2158490     Document Type: Article

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