-
1
-
-
29044450495
-
All-digital PLL and transmitter for mobile phone
-
Dec
-
R. B. Staszewski, J. Wallberg, S. Rezeq, C-M. Hung, O. Eliezer, S. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M.-C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold, "All-digital PLL and transmitter for mobile phone," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2469-2482, Dec. 2005.
-
(2005)
IEEE J. Solid-State Circuits
, vol.40
, Issue.12
, pp. 2469-2482
-
-
Staszewski, R.B.1
Wallberg, J.2
Rezeq, S.3
Hung, C.-M.4
Eliezer, O.5
Vemulapalli, S.6
Fernando, C.7
Maggio, K.8
Staszewski, R.9
Barton, N.10
Lee, M.-C.11
Cruise, P.12
Entezari, M.13
Muhammad, K.14
Leipold, D.15
-
2
-
-
85008054348
-
A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI
-
Jan
-
J. Tiero, A. Rylyakov, and D. Friedman, "A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 42-51, Jan. 2008.
-
(2008)
IEEE J. Solid-State Circuits
, vol.43
, Issue.1
, pp. 42-51
-
-
Tiero, J.1
Rylyakov, A.2
Friedman, D.3
-
3
-
-
49549102895
-
A fractional spur-free ADPLL with loop-gain calibration and phase-noise cancellation for GSM/GPRS/EDGE
-
H.-H. Chang, P.-Y. Wang, J.-H. Zhan, and B.-Y. Hsieh, "A fractional spur-free ADPLL with loop-gain calibration and phase-noise cancellation for GSM/GPRS/EDGE," in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 200-201.
-
(2008)
IEEE ISSCC Dig. Tech. Papers
, pp. 200-201
-
-
Chang, H.-H.1
Wang, P.-Y.2
Zhan, J.-H.3
Hsieh, B.-Y.4
-
4
-
-
57849164692
-
A low-noise wide-BW 3.6-GHz digital ΔΣfractional-N frequency synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation
-
Dec
-
C.-M. Hsu, M. Straayer, and M. H. Perrott, "A low-noise wide-BW 3.6-GHz digital ΔΣfractional-N frequency synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation," IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2776-2786, Dec. 2008.
-
(2008)
IEEE J. Solid-State Circuits
, vol.43
, Issue.12
, pp. 2776-2786
-
-
Hsu, C.-M.1
Straayer, M.2
Perrott, M.H.3
-
5
-
-
33644996419
-
1.3 V, 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS
-
Mar
-
R. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and B. P. T., "1.3 V, 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS," IEEE Trans. Cirvuits Syst. II, vol. 53, no. 3, pp. 2240-2244, Mar. 2006.
-
(2006)
IEEE Trans. Cirvuits Syst. II
, vol.53
, Issue.3
, pp. 2240-2244
-
-
Staszewski, R.1
Vemulapalli, S.2
Vallur, P.3
Wallberg, J.4
T, B.P.5
-
6
-
-
46749143423
-
90 nm 4.7 ps-resolution 0.7-LSB single-shot precision and 19 pJ-per-shot local passive interpolation time-to-digital converter with on-chip characterization
-
S. Henzler, S. Koeppe, W. Kamp, H. Mulatz, and D. Schmitt-Landsiedel, "90 nm 4.7 ps-resolution 0.7-LSB single-shot precision and 19 pJ-per-shot local passive interpolation time-to-digital converter with on-chip characterization," in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 548-549.
-
(2008)
IEEE ISSCC Dig. Tech. Papers
, pp. 548-549
-
-
Henzler, S.1
Koeppe, S.2
Kamp, W.3
Mulatz, H.4
Schmitt-Landsiedel, D.5
-
7
-
-
41549133070
-
A 9b, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue
-
Apr
-
M. Lee and A. Abidi, "A 9b, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 769-777, Apr. 2008.
-
(2008)
IEEE J. Solid-State Circuits
, vol.43
, Issue.4
, pp. 769-777
-
-
Lee, M.1
Abidi, A.2
-
8
-
-
49549112279
-
A 3 GHz fractional-N all-digital PLL with precise time-to-digital converter calibration and mismatch correction
-
C. Weltin-Wu, E. Temporiti, D. Baldi, and F. Svelto, "A 3 GHz fractional-N all-digital PLL with precise time-to-digital converter calibration and mismatch correction," in IEEEISSCC Dig. Tech. Papers, 2008, pp. 344-345.
-
(2008)
IEEEISSCC Dig. Tech. Papers
, pp. 344-345
-
-
Weltin-Wu, C.1
Temporiti, E.2
Baldi, D.3
Svelto, F.4
-
9
-
-
33748569088
-
A wide-range, high-resolution, compact, CMOS time to digital converter
-
Jan, 6 pp, online
-
V. Ramakrishnan and P. T. Balsara, "A wide-range, high-resolution, compact, CMOS time to digital converter," in VLSI Design (VLSID '06), Jan. 2006, 6 pp., online.
-
(2006)
VLSI Design (VLSID '06)
-
-
Ramakrishnan, V.1
Balsara, P.T.2
-
10
-
-
33746623994
-
A CMOS time-to-digital converter with better than 10 ps single-shot precision
-
Jun
-
J.-P. Jansson, A. Mantyniemi, and J. Kostamovaara, "A CMOS time-to-digital converter with better than 10 ps single-shot precision," IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1286-1296, Jun. 2006.
-
(2006)
IEEE J. Solid-State Circuits
, vol.41
, Issue.6
, pp. 1286-1296
-
-
Jansson, J.-P.1
Mantyniemi, A.2
Kostamovaara, J.3
-
11
-
-
39749105449
-
A low jitter 1.6 GHz multiplying DLL utilizing a scrambling time-to-digital converter and digital correlation
-
Jun
-
B. Helal, M. Straayer, and M. H. Perrott, "A low jitter 1.6 GHz multiplying DLL utilizing a scrambling time-to-digital converter and digital correlation," in VLSI Symp. Dig. Tech. Papers, Jun. 2007, pp. 166-167.
-
(2007)
VLSI Symp. Dig. Tech. Papers
, pp. 166-167
-
-
Helal, B.1
Straayer, M.2
Perrott, M.H.3
-
12
-
-
51949114983
-
An efficient high-resolution 11-bit noise-shaping multipath gated ring oscillator
-
Jun
-
M. Straayer and M. Perrott, "An efficient high-resolution 11-bit noise-shaping multipath gated ring oscillator," in VLSI Symp. Dig. Tech. Papers, Jun. 2008, pp. 82-83.
-
(2008)
VLSI Symp. Dig. Tech. Papers
, pp. 82-83
-
-
Straayer, M.1
Perrott, M.2
-
13
-
-
0026994034
-
A 2-chip 1.5 gigabaud serial link interface
-
Dec
-
R. Walker, C. Stout, J. Wu, B. Lai, C. Yen, T. Hornak, and P. Perruno, "A 2-chip 1.5 gigabaud serial link interface," IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1805-1811, Dec. 1992.
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, Issue.12
, pp. 1805-1811
-
-
Walker, R.1
Stout, C.2
Wu, J.3
Lai, B.4
Yen, C.5
Hornak, T.6
Perruno, P.7
-
14
-
-
33947615213
-
Statistical linearity calibration of time-to-digital converters using a free-running ring oscillator
-
Nov
-
J. Rivoir, "Statistical linearity calibration of time-to-digital converters using a free-running ring oscillator," in IEEE Asian Test Symp., Nov. 2006, pp. 45-50.
-
(2006)
IEEE Asian Test Symp
, pp. 45-50
-
-
Rivoir, J.1
-
15
-
-
4644316834
-
A CMOS time-to-digital converter based on a ring oscillator for a laser radar
-
Apr
-
I. Nissinen, A. Mantyniemi, and J. Kostamovaara, "A CMOS time-to-digital converter based on a ring oscillator for a laser radar," in Proc. IEEE ESSCIRC, Apr. 2003, pp. 469-472.
-
(2003)
Proc. IEEE ESSCIRC
, pp. 469-472
-
-
Nissinen, I.1
Mantyniemi, A.2
Kostamovaara, J.3
-
16
-
-
0029532111
-
Linearity enhancement of multibit delta-sigma A/D and D/A converters using data weighted averaging
-
Dec
-
R. Baird and T. Fiez, "Linearity enhancement of multibit delta-sigma A/D and D/A converters using data weighted averaging," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 42, no. 12, pp. 753-762, Dec. 1995.
-
(1995)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process
, vol.42
, Issue.12
, pp. 753-762
-
-
Baird, R.1
Fiez, T.2
-
17
-
-
0031075618
-
A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme
-
Feb
-
S. J. Lee, B. Kim, and K. Lee, "A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme," IEEE J. Solid-State Circuits, vol. 32, no. 2, pp. 289-291, Feb. 1997.
-
(1997)
IEEE J. Solid-State Circuits
, vol.32
, Issue.2
, pp. 289-291
-
-
Lee, S.J.1
Kim, B.2
Lee, K.3
-
18
-
-
33847131935
-
Differential ring oscillators with multipath delay stages
-
Sep
-
S. S. Mohan, W. S. Chan, D. M. Colleran, S. F. Greenwood, J. E. Gamble, and I. G. Kouznetsov, "Differential ring oscillators with multipath delay stages," in Proc. IEEE CICC, Sep. 2005, pp. 503-506.
-
(2005)
Proc. IEEE CICC
, pp. 503-506
-
-
Mohan, S.S.1
Chan, W.S.2
Colleran, D.M.3
Greenwood, S.F.4
Gamble, J.E.5
Kouznetsov, I.G.6
-
19
-
-
0027851095
-
Precise delay generation using coupled oscillators
-
Dec
-
J. G. Maneatis and M. A. Horowitz, "Precise delay generation using coupled oscillators," IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1273-1282, Dec. 1993.
-
(1993)
IEEE J. Solid-State Circuits
, vol.28
, Issue.12
, pp. 1273-1282
-
-
Maneatis, J.G.1
Horowitz, M.A.2
-
20
-
-
41549143170
-
A design method and developments of a low-power and high-resolution multiphase generation system
-
Apr
-
A. Matsumoto, S. Sakiyama, Y. Tokunaga, T. Morie, and S. Dosho, "A design method and developments of a low-power and high-resolution multiphase generation system," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 831-843, Apr. 2008.
-
(2008)
IEEE J. Solid-State Circuits
, vol.43
, Issue.4
, pp. 831-843
-
-
Matsumoto, A.1
Sakiyama, S.2
Tokunaga, Y.3
Morie, T.4
Dosho, S.5
-
21
-
-
57849152393
-
Noise shaping techniques for analog and time to digital converters using voltage controlled oscillators,
-
Ph.D. dissertation, MIT, Cambridge, MA
-
M. Straayer, "Noise shaping techniques for analog and time to digital converters using voltage controlled oscillators," Ph.D. dissertation, MIT, Cambridge, MA, 2008.
-
(2008)
-
-
Straayer, M.1
|