Two-dimensions vernier time-to-digital converter

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 8, 2010, Pages 1504-1512

  Vercesi, Luca ^a   Liscidini, Antonio ^a   Castello, Rinaldo ^a  

^a UNIVERSITY OF PAVIA   (Italy)

Author keywords

All digital PLL; TDC calibration; time to digital converter; Vernier

Indexed keywords

65NM CMOS TECHNOLOGY; ALL DIGITAL PLL; CONVERSION RATES; DELAY LINE; DIGITAL CONVERSION; LINEAR APPROACH; POWER CONSUMPTION; TIME RESOLUTION; TIME TO DIGITAL CONVERTERS; VERNIER TDC;

CALIBRATION; CMOS INTEGRATED CIRCUITS; ELECTRIC DELAY LINES; WAVES;

FREQUENCY CONVERTERS;

EID: 77955163691     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2047435     Document Type: Conference Paper

References (12)

1. E. Temporiti, C. Weltin-Wu, D. Baldi, R. Tonietto, and F. Svelto, "A 3 GHz fractional all-digital PLL with a 1.8 MHz bandwidth implementing spur reduction techniques," IEEE J. Solid-State Circuits, vol.44, no.3, pp. 824-834, Mar. 2009.
2. R. B. Staszewski, S. K. Vemulapalli, P. Vallur, J. L.Wallberg, and P. T. Balsara, "1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS," IEEE Trans. Circuits Syst. II, Express Briefs, vol.53, no.3, pp. 220-224, Mar. 2006.
3. P. Dudek, S. Szczepanski, and J. Hatfield, "A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line," IEEE J. Solid- State Circuits, vol.35, no.2, pp. 240-247, Feb. 2007.
4. S. Henzler, S. Koeppe, W. Kamp, H. Mulatz, and D. Schmitt-Landsiedel, "90 nm 4.7 ps-resolution 0.7-LSB single-shot precision and 19 pJ-per-shot local passive interpolation time-to-digital converter with on-chip characterization," in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 548-549.
5. K. Nose, M. Kajita, and M. Mizuno, "A 1-ps resolution jitter measurement macro using interpolated jitter oversampling," IEEE J. Solid-State Circuits, vol.41, no.12, pp. 2911-2920, Dec. 2006. (Pubitemid 44955516)
6. R. Tonietto, E. Zuffetti, R. Castello, and I. Bietti, "A 3MHz bandwidth low noise RF all digital PLL with 12 ps resolution time to digital converter," in Proc. ESSCIRC, Sep. 2006, pp. 150-153.
7. J.-P. Tignol, Galois' Theory of Algebraic Equations. Singapore: World Scientific, 2001.
8. M. Lee and A. A. Abidi, "A 9 b 1.25 ps resolution coarse-fine time-todigital converter in 90 nm CMOS that amplifies a time residue," IEEE J. Solid-State Circuits, vol.43, no.4, pp. 769-777, Apr. 2008.
9. J.-P. Jansson, A. Mantyniemi, and J. Kostamovaara, "A CMOS time-to-digital converter with better than 10 ps single-shot precision," IEEE J. Solid-State Circuits, vol.41, no.6, pp. 1286-1296, Jun. 2006.
10. M. Straayer and M. Perrott, "A multi-path gated ring oscillator TDC with first-order noise shaping," IEEE J. Solid-State Circuits, vol.44, no.4, pp. 1089-1098, Apr. 2009.
11. H. Matsumura, Commutative Ring Theory. New York: Cambridge University Press, 1986.
12. A. Mäntyniemi, T. Rahkonen, and J. Kostamovaara, "A CMOS time-to-digital converter (TDC) based on a cyclic time domain successive approximation interpolation method," IEEE J. Solid-State Circuits, vol.44, no.11, pp. 3067-3078, Nov. 2009.