-
3
-
-
52449145649
-
Floorplan design of VLSI circuits
-
D. F. Wong and C. L. Liu, "Floorplan Design of VLSI Circuits," Algorithmica, vol. 4, pp. 263-291, 1989.
-
(1989)
Algorithmica
, vol.4
, pp. 263-291
-
-
Wong, D.F.1
Liu, C.L.2
-
4
-
-
0030378255
-
VLSI module placement based on rectangle packing by the sequence-pair
-
Dec.
-
H. Murata, F. Fujiyoshi, S. Nakatake, Y. Kajitani, "VLSI Module Placement based on Rectangle Packing by the Sequence-Pair," IEEE Transactions on Computer-Aided Design, vol. 15, pp. 1518-1524, Dec. 1996.
-
(1996)
IEEE Transactions on Computer-Aided Design
, vol.15
, pp. 1518-1524
-
-
Murata, H.1
Fujiyoshi, F.2
Nakatake, S.3
Kajitani, Y.4
-
5
-
-
0032090672
-
Module packing based on the BSG-structure and IC layout applications
-
June
-
S. Nakatake, F. Fujiyoshi, H. Murata, Y. Kajitani, "Module Packing Based on the BSG-Structure and IC Layout Applications," IEEE Transactions on Computer-Aided Design, vol. 17, pp. 519-530, June 1998.
-
(1998)
IEEE Transactions on Computer-Aided Design
, vol.17
, pp. 519-530
-
-
Nakatake, S.1
Fujiyoshi, F.2
Murata, H.3
Kajitani, Y.4
-
6
-
-
0033704928
-
An enhanced perturbing algorithm for floorplan design using the O-tree representation
-
Y. Pang, C.-K. Cheng and T. Yoshimura, "An Enhanced Perturbing Algorithm for Floorplan Design Using the O-tree Representation," in ISPD 2000. pp. 168-173.
-
(2000)
ISPD 2000
, pp. 168-173
-
-
Pang, Y.1
Cheng, C.-K.2
Yoshimura, T.3
-
7
-
-
0033701594
-
B*-trees: A new representation for non-slicing floorplans
-
Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu, "B*-Trees: A New Representation for Non-Slicing Floorplans," in DAC 2000, pp. 103-110.
-
(2000)
DAC 2000
, pp. 103-110
-
-
Chang, Y.-C.1
Chang, Y.-W.2
Wu, G.-M.3
Wu, S.-W.4
-
9
-
-
0034481271
-
Corner block list: An effective and efficient topological representation of non-slicing floorplan
-
X. Hong et al, "Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan," in ICCAD 2000, pp. 8-13.
-
(2000)
ICCAD 2000
, pp. 8-13
-
-
Hong, X.1
-
10
-
-
11144243619
-
On the use of flexible, rectilinear blocks to obtain minimum-area floorplans in mixed block and cell designs
-
Jan.
-
D. Mehta and N. Sherwani, "On the use of Flexible, Rectilinear Blocks to obtain Minimum-area Floorplans in Mixed Block and Cell Designs," ACM Transactions on Design Automation of Electronic Systems, vol. 5, pp. 82-97, Jan. 2000.
-
(2000)
ACM Transactions on Design Automation of Electronic Systems
, vol.5
, pp. 82-97
-
-
Mehta, D.1
Sherwani, N.2
-
11
-
-
23044526631
-
Constrained polygon transformations for incremental floorplanning
-
S. Liao, M. Lopez, and D. Mehta, "Constrained Polygon Transformations for Incremental Floorplanning," ACM Transactions on Design Automation of Electronic Systems, vol. 6, July 2001.
-
(2001)
ACM Transactions on Design Automation of Electronic Systems
, vol.6
-
-
Liao, S.1
Lopez, M.2
Mehta, D.3
-
13
-
-
0036377317
-
Consistent placement of macro-blocks using flooplanning and standard-cell placement
-
S.N. Adya, I.L. Markov, "Consistent Placement of Macro-blocks Using Flooplanning and Standard-Cell Placement," in ISPD 2002.
-
(2002)
ISPD 2002
-
-
Adya, S.N.1
Markov, I.L.2
-
16
-
-
0004116989
-
-
New York: McGraw-Hill
-
T.H. Cormen, C.E. Leiserson, R.L. Rivest and C. Stein, Introduction to Algorithms, Second Edition. New York: McGraw-Hill, 2001.
-
(2001)
Introduction to Algorithms, Second Edition
-
-
Cormen, T.H.1
Leiserson, C.E.2
Rivest, R.L.3
Stein, C.4
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