Adaptive voltage over-scaling for resilient applications

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2011, Pages 944-949

  Krause, Philipp Klaus ^a   Polian, Ilia ^b  

^a GOETHE UNIVERSITY   (Germany)

^b UNIVERSITY OF PASSAU   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE VOLTAGE; ENERGY REDUCTION; ERROR RECOVERY; HARDWARE BLOCKS; LOSSY COMPRESSIONS; PROCESS VARIATION; QUALITY LOSS;

ELECTRIC POTENTIAL; VOLTAGE REGULATORS;

ERROR DETECTION;

EID: 79957556496     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (36)

1. A. Chandrakasan and R. Brodersen, "Minimizing power consumption in digital CMOS circuits," Proc. IEEE, vol. 83, no. 4, pp. 498-523, 1995.
2. P. Pillai and K. Shin, "Real-time dynamic voltage scaling for low-power embedded operating systems," in ACM Symp. on Operating Systems Principles, 2001, pp. 89-102.
3. M. A. Breuer, "Multi-media applications and imprecise computation," in Euromicro Conf., 2005, pp. 2-7.
4. X. Li and D. Yeung, "Application-level correctness and its impact on fault tolerance," in HPCA, 2007, pp. 181-192.
5. J. Liu et al., "Imprecise computations," Proc. IEEE, vol. 82, no. 1, pp. 83-94, 1994.
6. D. Nowroth, I. Polian, and B. Becker, "A study of cognitive resilience in a JPEG compressor," in DSN, 2008, pp. 32-41.
7. D. Ernst et al., "Razor: A low-power pipeline based on circuit-level timing speculation," in Int'l Symp. on Microarchitecture, 2003, p. 7.
8. P. Krause, "ftc-floating precision texture compression," Computers & Graphics, vol. 34, no. 5, pp. 594-601, 2010.
9. J. George, B. Marr, B. Akgul, and K. Palem, "Probabilistic arithmetic and energy efficient embedded signal processing," in CASES, 2006.
10. G. Varatkar and N. Shanbhag, "Error-resilient motion estimation architecture," IEEE Trans. VLSI, vol. 16, no. 10, pp. 1399-1412, 2008.
11. P. Brown and M. Agopian, "EXT-texture-compression-dxt1," http://opengl.org/registry/specs/EXT/texture-compression-dxt1.txt.
12. D. Bull and S. Das, "Latch to block short path violation," 2008, US Patent 2008/0086624 A1.
13. "OSU design flows for MOSIS SCMOS-SUBM design flow FreePDK 45nm variation-aware design flow," http://vcag.ecen.okstate.edu/projects/scells/ .
14. A. Davis, "An overview of algorithms in gnucap," in University/ Government/Industry Microelectronics Symp., 2003, pp. 360-361.
15. J. Le, X. Li, and L. Pileggi, "STAC: Statistical timing analysis with correlation," in DAC, 2004, pp. 343-348.
16. Y. Kawakami et al., "A power grid optimization algorithm by observing timing error risk by IR drop," IEICE Transactions, vol. 91-A, no. 12, pp. 3423-3430, 2008.
17. A. Agarwal, D. Blaauw, and V. Zolotov, "Statistical timing analysis for intra-die process variations with spatial correlations," in ICCAD, 2003, p. 900.
18. D. Iparraguirre-Cardenas, J. Garcia-Gervacio, and V. Champac, "A design methodology for logic paths tolerant to local intra-die variations," in ISCAS, 2008, pp. 596-599.
19. S.-T. Cheng and R. Brayton, "Compiling Verilog into Automata, UCB ERL Technical Report M94/37," 1994.
20. R. Brayton et al., "VIS: A system for verification and synthesis," in Formal Methods in CAD, 1996, pp. 428-432.
21. Berkeley Logic Synthesis and Verification Group, "ABC: A system for sequential synthesis and verification, release 70930," http://www.eecs. berkeley.edu/ alanmi/abc/.
22. S. Williams and M. Baxter, "Icarus Verilog: open-source Verilog more than a year later," Linux Jour., vol. 2002, no. 99, p. 3, 2002.
23. A. Loza et al., "Structural similarity-based object tracking in video sequences," in Int'l Conf. on Information Fusion, 2006, pp. 1-6.
24. Z. Wang et al., "Image quality assessment: from error visibility to structural similarity," IEEE Trans. Image Processing, vol. 13, no. 4, pp. 600-612, 2004.
25. P. Krause, "C++ implementation of DSSIM," http://colecovision. eu/graphics/DSSIM/.
26. C. Gauss, "Theoria combinationis observationum erroribus minimis obnoxiae," Commentationes Societatis Regiae Scientiarum Gottingensis recentiores, vol. 5, pp. 33-90, 1823.
27. G. Ohm, Die galvanische Kette, 1827.
28. J. Pouwelse, K. Langendoen, and H. Sips, "Dynamic voltage scaling on a low-power microprocessor," in Int'l Conf. Mobile Comp.&Netw., 2001.
29. S. Ghosh, S. Bhunia, and K. Roy, "CRISTA: A new paradigm for lowpower, variation-tolerant, and adaptive circuit synthesis using critical path isolation," IEEE Trans. CAD, vol. 26, no. 11, pp. 1947-1956, 2007.
30. R. Hegde and N. Shanbhag, "Soft digital signal processing," IEEE Trans. VLSI, vol. 9, no. 6, pp. 813-823, 2001.
31. -, "A voltage overscaled low-power digital filter IC," IEEE Jour. Solid-State Circuits, vol. 39, no. 2, pp. 388-391, 2004.
32. J. Natarajan, G. Kumar, S. Sen, M. Nisar, D. Lee, and A. Chatterhee, "Aggressively voltage overscaled adaptive RF systems using error control at the bit and symbol levels," in IOLTS, 2009, pp. 249-254.
33. A. Kahng et al., "Designing a processor from the ground up to allow voltage/reliability tradeoffs," in HPCA, 2010.
34. N. Banerjee et al., "Design methodology for low power and parametric robustness through output-quality modulation: Application to color-interpolation filtering," IEEE Trans. CAD, vol. 28, no. 8, pp. 1127-1137, 2009.
35. L. Chakrapani et al., "Highly energy and performance efficient embedded computing through approximately correct arithmetic," in CASES, 2008.
36. P. Subramanyan et al., "Power efficient redundant execution for chip multiprocessors," in Works. Depend. & Secure Nanocomputing, 2009.