Design methodology for low power and parametric robustness through output-quality modulation: Application to color-interpolation filtering

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 28, Issue 1, 2009, Pages 1127-1137

  Banerjee, Nilanjan ^a   Karakonstantis, Georgios ^a   Choi, Jung Hwan ^a   Chakrabarti, Chaitali ^b   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

^b Arizona State University   (United States)

Author keywords

Color interpolation; Low power design; Process variation tolerance; Quality Vdd tradeoffs

Indexed keywords

COLOR INTERPOLATION; DELAY VARIATION; DESIGN METHODOLOGY; DESIGN REQUIREMENTS; GRACEFUL DEGRADATION; INTERPOLATION FILTERING; LOW POWER; LOW-POWER DESIGN; OUTPUT QUALITY; PEAK SIGNAL-TO-NOISE RATIO; PIXEL VALUES; POWER DISSIPATION; POWER SAVINGS; PROCESS VARIATION; SIMULATION RESULT; SLIDING-WINDOW; UPSCALING; VARIATION TOLERANCES; VOLTAGE-SCALING;

COLOR; DESIGN; SIGNAL TO NOISE RATIO;

INTERPOLATION;

EID: 77955224498     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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