Error-resilient motion estimation architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 16, Issue 10, 2008, Pages 1399-1412

  Varatkar, Girish Vishnu ^a   Shanbhag, Naresh R ^a  

^a United States of America   (United States)

Author keywords

Algorithmic noise tolerance; Error tolerant design; Low power design; Motion estimation; Process variation tolerance

Indexed keywords

ARCHITECTURAL DESIGN; ARCHITECTURE; CONSERVATION; ENERGY CONSERVATION; ENERGY EFFICIENCY; ERRORS; ESTIMATION; MOTION ESTIMATION; SIGNAL TO NOISE RATIO;

ALGORITHMIC NOISE-TOLERANCE; AVERAGE-CASE; CMOS TECHNOLOGIES; ENERGY-EFFICIENT; ERROR-RESILIENT; ERROR-TOLERANT DESIGN; LOW POWER DESIGN; NOISE-TOLERANCE; OPTIMAL ERROR; PEAK SIGNAL-TO-NOISE RATIO; POWER REDUCTIONS; POWER SAVINGS; PREDICTIVE PROCESSES; PROCESS TECHNOLOGIES; PROCESS VARIATION-TOLERANCE; PROCESS VARIATIONS; PROPOSED ARCHITECTURES; SUPPLY VOLTAGES; TIMING ERRORS; VOLTAGE OVERSCALING;

TECHNOLOGY;

EID: 52649112190     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2000675     Document Type: Conference Paper

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