A design methodology for logic paths tolerant to local intra-die variations

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2008, Pages 596-599

  Iparraguirre Cárdenas, Daniel ^a   García Gervacio, José L ^a   Champac, Víctor ^a  

^a INSTITUTO NACIONAL DE ASTROFÍSICA   (Mexico)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; TECHNICAL PRESENTATIONS;

DELAY VARIABILITY; PERFORMANCE DISTRIBUTION; PROCESS VARIATIONS;

DIGITAL CIRCUITS;

EID: 51749117162     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2008.4541488     Document Type: Conference Paper

References (10)

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2. J. Tschanz et al, "Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage", IEEE journal of Solid-State Circuits, vol. 37, pp. 1396-1402, Nov. 2002.
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