A voltage overscaled low-power digital filter IC

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 2, 2004, Pages 388-391

  Hegde, Rajamohana ^a   Shanbhag, Naresh R ^b  

^a Intersymbol Communications Inc   (United States)

^b University of Illinois at Urbana Champaign   (United States)

Author keywords

Error control; Low power; Voltage overscaling

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; DIGITAL FILTERS; ERROR CORRECTION; FIR FILTERS; LOW PASS FILTERS; SIGNAL TO NOISE RATIO; SPURIOUS SIGNAL NOISE;

ALGORITHMIC NOISE TOLERANCE; ERROR CONTROL TECHNIQUE; LOW POWER DIGITAL FILTER; VOLTAGE OVERSCALING;

INTEGRATED CIRCUIT LAYOUT;

EID: 1242263405     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.821775     Document Type: Article

References (6)

1. A. Chandrakasan and R. W. Brodersen, "Minimizing power consumption in digital CMOS circuits," Proc. IEEE, vol. 83, pp. 498-523, Apr. 1995.
2. R. Gonzalez, B. M. Gordon, and M. A. Horowitz, "Supply and threshold voltage scaling for low power CMOS," IEEE J. Solid-State Circuits, vol. 32, pp. 1210-1216, Aug. 1997.
3. A. Sinha and A. Chandrakasan, "Energy efficient filtering using adaptive precision and variable voltage," in Proc. 1999 ASIC/SOC Conf., pp. 327-331.
4. R. Hegde and N. R. Shanbhag, "Soft digital signal processing," IEEE Trans. VLSI, vol. 9, pp. 813-823, Dec. 2001.
5. J. G. Proakis and D. G. Manolakis, Digital Signal Processing: Principles, Algorithms and Applications. Englewood Cliffs, NJ: Prentice-Hall, 1996.
6. J. M. Rabaey, Digital Integrated Circuits: A Design Perspective. Englewood Cliffs, NJ: Prentice-Hall, 1996.