A power grid optimization algorithm by observing timing error risk by IR drop

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E91-A, Issue 12, 2008, Pages 3423-3430

  Kawakami, Yoshiyuki ^a   Terao, Makoto ^a   Fukui, Masahiro ^a   Tsukiyama, Shuji ^b  

^a RITSUMEIKAN UNIVERSITY   (Japan)

^b CHUO UNIVERSITY   (Japan)

Author keywords

Critical path; IR drop; Power grid optimization; Process variation; Timing violation

Indexed keywords

DELAY CIRCUITS; DROPS; ELECTRIC NETWORK ANALYSIS; ERRORS; OPTIMIZATION; SYSTEM-ON-CHIP; TIMING CIRCUITS;

CRITICAL PATHS; IR DROP; POWER GRIDS; PROCESS VARIATION; TIMING VIOLATION;

ELECTRIC POWER TRANSMISSION NETWORKS;

EID: 77951561017     PISSN: 09168508     EISSN: 17451337     Source Type: Journal    
DOI: 10.1093/ietfec/e91-a.12.3423     Document Type: Article

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