ACCESS: Smart scheduling for asymmetric cache CMPs

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2011, Pages 527-538

  Jiang, Xiaowei ^a   Mishra, Asit ^b   Zhao, Li ^a   Iyer, Ravishankar ^a   Fang, Zhen ^a   Srinivasan, Sadagopan ^a   Makineni, Srihari ^a   Brett, Paul ^a   Das, Chita R ^b  

^a INTEL CORPORATION   (United States)

^b PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE CAPACITY; CACHE PERFORMANCE; CHIP MULTIPROCESSOR; HARDWARE SUPPORTS; HARDWARE/SOFTWARE; MULTIPLE APPLICATIONS; PERFORMANCE IMPROVEMENTS; PREDICTION CAPABILITY; VIRTUAL MACHINES;

COMPUTER ARCHITECTURE;

SCHEDULING;

EID: 79955903988     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2011.5749757     Document Type: Conference Paper

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