CHOP: Integrating DRAM caches for CMP server platforms

IEEE Micro

Volumn 31, Issue 1, 2011, Pages 99-108

  Jiang, Xiaowei ^a   Madan, Niti ^b   Zhao, Li ^a   Upton, Mike ^a   Iyer, Ravi ^a   Makineni, Srihari ^a   Newell, Don ^a   Solihin, Yan ^c   Balasubramonian, Rajeev ^d  

^a INTEL CORPORATION   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c NORTH CAROLINA STATE UNIVERSITY   (United States)

^d UNIVERSITY OF UTAH   (United States)

Author keywords

cache memories; CHOP; DRAM; emerging technologies; filter cache; hardware; hot pages; memory hierarchy

Indexed keywords

CHOP; DRAM; EMERGING TECHNOLOGIES; FILTER CACHE; HOT PAGES; MEMORY HIERARCHY;

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DYNAMIC RANDOM ACCESS STORAGE;

CACHE MEMORY;

EID: 79951840672     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2010.100     Document Type: Article

References (11)

1. D. Burger, J.R. Goodman, and A. Kägi, "Memory Bandwidth Limitations of Future Microprocessors," Proc. 23rd Ann. Int'l Symp. Computer Architecture (ISCA 96), ACM Press, 1996, pp. 78-79.
2. F. Liu et al., "Understanding How Off-Chip Memory Bandwidth Partitioning in Chip-Multiprocessors Affects System Performance," Proc. IEEE 16th Int'l Symp. High Performance Computer Architecture (HPCA 10), IEEE Press, 2010, doi:10.1109/HPCA.2010.5416655.
3. B.M. Rogers et al., "Scaling the Bandwidth Wall: Challenges in and Avenues for CMP Scaling," Proc. 36th Ann. Int'l Symp. Computer Architecture (ISCA 09), ACM Press, 2009, pp. 371-382.
4. B. Black et al., "Die Stacking (3D) Microarchitecture," Proc. 39th Int'l Symp. Microarchitecture, IEEE CS Press, 2006, pp. 469-479. (Pubitemid 351337019)
5. R. Iyer, "Performance Implications of Chipset Caches in Web Servers," Proc. IEEE Int'l Symp. Performance Analysis of Systems and Software (ISPASS 03), IEEE CS Press, 2003, pp. 176-185.
6. th Int'l Symp. High Performance Computer Architecture (HPCA 09), IEEE Press, 2009, pp. 262-274.
7. Z. Zhang, Z. Zhu, and X. Zhang, "Design and Optimization of Large Size and Low Overhead Off-Chip Caches," IEEE Trans. Computers, vol. 53, no. 7, 2004, pp. 843-855.
8. L. Zhao et al., "Exploring DRAM Cache Architectures for CMP Server Platforms," Proc. 25th Int'l Conf. Computer Design (ICCD 07), IEEE Press, 2007, pp. 55-62.
9. X. Jiang et al., "CHOP: Adaptive Filter-Based DRAM Caching for CMP Server Platforms," Proc. IEEE 16th Int'l Symp. High Performance Computer Architecture (HPCA 10), IEEE Press, 2010, doi:10.1109/HPCA.2010.5416642
10. Intel Architecture Software Developer's Manual, vol. 1, Intel, 2008; http://www.intel.com/design/pentiumii/manuals/243190.htm.
11. L. Zhao et al., "Exploring Large-Scale CMP Architectures Using ManySim," IEEE Micro, vol. 27, no. 4, 2007, pp. 21-33. (Pubitemid 47595641)