Architecture support for improving bulk memory copying and initialization performance

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2009, Pages 169-180

  Jiang, Xiaowei ^a   Solihin, Yan ^a   Zhao, Li ^b   Iyer, Ravishankar ^b  

^a North Carolina State University   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Cache affinity; Cache neutral; Early retirement; Memory copying; Memory initialization

Indexed keywords

BUFFER MANAGEMENT; CACHE ACCESS; CACHE AFFINITY; CRITICAL PATHS; CURRENT SYSTEM; OPERATING SYSTEMS; PIPELINE RESOURCES; SPEEDUP RATIO;

COMPUTER OPERATING SYSTEMS; PARALLEL ARCHITECTURES; PIPELINE CODES; PIPELINES;

CACHE MEMORY;

EID: 70449658281     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2009.31     Document Type: Conference Paper

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