Cost-sensitive cache replacement algorithms

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn 12, Issue , 2003, Pages 327-337

  Jeong, J ^a   Dubois, M ^b  

^a IBM   (United States)

^b University of Southern California ^*  (United States)

Author keywords

Aggregates; Bandwidth; Computer architecture; Cost function; Delay; Energy consumption; Heuristic algorithms; Multiprocessing systems; Switches

Indexed keywords

AGGREGATES; ALGORITHMS; BANDWIDTH; CACHE MEMORY; COMPUTER ARCHITECTURE; COST FUNCTIONS; ENERGY UTILIZATION; HEURISTIC ALGORITHMS; MULTIPROCESSING SYSTEMS; SUPERCOMPUTERS; SWITCHES;

BANDWIDTH CONSUMPTION; CACHE REPLACEMENT ALGORITHM; DELAY; NUMERICAL PROPERTIES; PARALLEL APPLICATION; SUPERSCALAR PROCESSOR; TRACE DRIVEN SIMULATION; UNIPROCESSOR SYSTEMS;

COSTS;

EID: 84955487178     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2003.1183550     Document Type: Conference Paper

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