Opportunities for optics in integrated circuits applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages 86-87

  Miller, D A B ^a   Bhatnagar, A ^a   Palermo, S ^a   Emami Neyestanak, A ^a   Horowitz, M A ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144459398     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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2. D.A.B. Miller, "Rationale and Challenges for Optical Interconnects to Electronic Chips," Proc. IEEE, vol 88, pp. 728-749, 2000.
3. G.A. Keeler et al., "The Benefits of Ultrashort Optical Pulses in Optically-Interconnected Systems," IEEE J. Sel. Top. Quantum Electron. vol. 9, pp. 477-485, 2003.
4. B.E. Nelson et al., "Wavelength Division Multiplexed Optical Interconnect Using Short Pulses," IEEE J. Sel. Top. Quantum Electron., vol. 9, pp. 486-491, 2003.
5. C. Debaes et al., "Receiver-less Optical Clock Injection for Clock Distribution Networks," IEEE J. Sel. Top. Quantum Electron., vol. 9, pp. 400-409, 2003.
6. R. Urata et al., "Photonic A/D Conversion Using Low-Temperature- Grown GaAs MSM Switches Integrated With Si-CMOS," J. Lightwave Technology, vol. 21, pp. 3104-3115, 2003.
7. A. Bhatnagar et al., "Pump-Probe Measurements of CMOS Detector Rise Time in the Blue," J. Lightwave Technology, vol. 22, pp. 2213-2217, Sept., 2004.
8. C.-K. Yang, M. Horowitz, "A 0.8-μm CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links," IEEE J. Solid-State Circuits, vol. 31, pp. 2015-2023, Dec., 1996.
9. K.-Y. K. Chang et al., "A 0.4-4-Gb/s CMOS Quad Transceiver Cell Using On-Chip Regulated Dual-Loop PLLs," IEEE J. Solid-State Circuits, vol. 38, pp. 747-754, May, 2003.
10. A. Emami-Neyestanak et al., "CMOS Transceiver with Baud Rate Clock Recovery for Optical Interconnects," Symp. VLSI Circuits, pp. 410-413, June, 2004.