Accurate, pre-RTL temperature-aware design using a parameterized, geometric thermal model

IEEE Transactions on Computers

Volumn 57, Issue 9, 2008, Pages 1277-1288

  Huang, Wei ^a   Sankaranarayanan, Karthik ^a   Skadron, Kevin ^a   Ribando, Robert J ^a   Stan, Mircea R ^a  

^a University of Virginia   (United States)

Author keywords

Compact thermal model; Early design stages; Leakage; Parameterized model; Temperature; Thermally optimized design flow

Indexed keywords

BOUNDARY CONDITIONS; BOUNDARY VALUE PROBLEMS; NONMETALS; OPTIMIZATION; SILICON; STAGES; THERMOGRAPHY (TEMPERATURE MEASUREMENT); WEIGHT CONTROL;

ACCURATE DESIGN; BOUNDARY CONDITIONING; CIRCUIT DESIGNERS; COMMUNICATION MEDIUM; COMPACT THERMAL MODEL; COMPACT THERMAL MODELING; COMPUTER ARCHITECTS; DESIGN CONVERGENCE; DESIGN CYCLES; DESIGN FLOWS; EARLY DESIGN STAGES; EXTREME CONDITIONS; FINITE ELEMENTS; HOT SPOTTING; LEAKAGE; MICROPROCESSOR DESIGNS; MODELING PACKAGES; OPTIMIZED DESIGNS; PACKAGE DESIGNERS; PARAMETERIZED; PARAMETERIZED MODEL; REAL-WORLD; SILICON CHIPS; TEMPERATURE; TEMPERATURE ESTIMATIONS; TEMPERATURE MODELLING; TEMPERATURE-AWARE DESIGN; THERMAL EFFECTS; THERMAL MODELLING; THERMAL RUNAWAY; THERMAL SIMULATION; THERMALLY OPTIMIZED DESIGN FLOW;

FINITE ELEMENT METHOD;

EID: 49149120280     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2008.64     Document Type: Article

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