-
1
-
-
33847734326
-
High performance 5nm radius Twin Silicon nanowire MOSFET(TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability
-
1609453, IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest
-
S. D. Suk, S.-Y. Lee, S.-M Kim, E.-J. Yoon, M.-S. Kim, M. Li, C. W. Oh, K. H. Yeo, S. H. Kim, D.-S. Shin, K.-H. Lee, H. S. Park, J. N. Han, C. J. Park, J.-B. Park, D.-W. Kim, D. Park, and B.-I. Ryu, "High performance 5 nm radius twin silicon nanowire MOSFET (TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability," in IEDM Tech. Dig., 2005, pp. 717-720. (Pubitemid 46370951)
-
(2005)
Technical Digest - International Electron Devices Meeting, IEDM
, vol.2005
, pp. 717-720
-
-
Suk, S.D.1
Lee, S.-Y.2
Kim, S.-M.3
Yoon, E.-J.4
Kim, M.-S.5
Li, M.6
Oh, C.W.7
Yeo, K.H.8
Kim, S.H.9
Shin, D.-S.10
Lee, K.-H.11
Park, H.S.12
Han, J.N.13
Park, C.J.14
Park, J.-B.15
Kim, D.-W.16
Park, D.17
Ryu, B.-I.18
-
2
-
-
46049102044
-
Gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 15 nm length gate and 4 nm radius nanowires
-
K. H. Yeo, S. D. Suk, M. Li, Y.-Y. Yeoh, K. H. Cho, K.-H. Hong, S. K. Yun, M. S. Lee, N. M. Cho, K. H. Lee, D. H. Hwang, B. K. Park, D.-W. Kim, D. Park, and B.-I. Ryu, "Gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 15 nm length gate and 4 nm radius nanowires," in IEDM Tech. Dig., 2006, pp. 1-4.
-
(2006)
IEDM Tech. Dig.
, pp. 1-4
-
-
Yeo, K.H.1
Suk, S.D.2
Li, M.3
Yeoh, Y.-Y.4
Cho, K.H.5
Hong, K.-H.6
Yun, S.K.7
Lee, M.S.8
Cho, N.M.9
Lee, K.H.10
Hwang, D.H.11
Park, B.K.12
Kim, D.-W.13
Park, D.14
Ryu, B.-I.15
-
3
-
-
50249161949
-
Investigation of nanowire size dependency on TSNWFET
-
S. D. Suk, M. Li, Y. Y. Yeoh, K. H. Yeo, K. H. Cho, I. K. Ku, H. Cho, W. J. Jang, D.-W. Kim, D. Park, and W.-S. Lee, "Investigation of nanowire size dependency on TSNWFET," in IEDM Tech. Dig., 2007, pp. 891-894.
-
(2007)
IEDM Tech. Dig.
, pp. 891-894
-
-
Suk, S.D.1
Li, M.2
Yeoh, Y.Y.3
Yeo, K.H.4
Cho, K.H.5
Ku, I.K.6
Cho, H.7
Jang, W.J.8
Kim, D.-W.9
Park, D.10
Lee, W.-S.11
-
4
-
-
43549111947
-
Gate-all-around twin silicon nanowire SONOS memory
-
S. D. Suk, K. H. Yeo, K. H. Cho, M. Li, Y. Y. Yeoh, K.-H. Hong, S.-H. Kim, Y.-H. Koh, S. G. Jung, W. J. Jang, D.-W. Kim, D. Park, and R.-I. Ryu, "Gate-all-around twin silicon nanowire SONOS memory," in Proc. VLSI Symp. Tech. Dig., 2007, pp. 142-143.
-
(2007)
Proc. VLSI Symp. Tech. Dig.
, pp. 142-143
-
-
Suk, S.D.1
Yeo, K.H.2
Cho, K.H.3
Li, M.4
Yeoh, Y.Y.5
Hong, K.-H.6
Kim, S.-H.7
Koh, Y.-H.8
Jung, S.G.9
Jang, W.J.10
Kim, D.-W.11
Park, D.12
Ryu, R.-I.13
-
5
-
-
51949099572
-
TSNWFET for SRAM cell application: Performance variation and process dependency
-
S. D. Suk, Y. Y. Yeoh, M. Li, K. H. Yeo, S.-H. Kim, D.-W. Kim, D. Park, and W.-S. Lee, "TSNWFET for SRAM cell application: Performance variation and process dependency," in Proc. VLSI Symp. Tech. Dig., 2008, pp. 38-39.
-
(2008)
Proc. VLSI Symp. Tech. Dig.
, pp. 38-39
-
-
Suk, S.D.1
Yeoh, Y.Y.2
Li, M.3
Yeo, K.H.4
Kim, S.-H.5
Kim, D.-W.6
Park, D.7
Lee, W.-S.8
-
6
-
-
58149505690
-
Investigation of low-frequency noise in silicon nanowire MOSFETs
-
Jan.
-
J. Zhuge, R. Wang, R. Huang, Y Tian, L. Zhang, D.-W. Kim, D. Park, and Y. Wang, "Investigation of low-frequency noise in silicon nanowire MOSFETs," IEEE Electron Device Lett., vol. 30, no. 1, pp. 57-60, Jan. 2009.
-
(2009)
IEEE Electron Device Lett.
, vol.30
, Issue.1
, pp. 57-60
-
-
Zhuge, J.1
Wang, R.2
Huang, R.3
Tian, Y.4
Zhang, L.5
Kim, D.-W.6
Park, D.7
Wang, Y.8
-
7
-
-
2942618387
-
Low-frequency noise assessment for deep submicrometer CMOS technology nodes
-
C. Claeys, A. Mercha, and E. Simoen, "Low-frequency noise assessment for deep submicrometer CMOS technology nodes," J. Electrochem. Soc., vol. 151, pp. G307-G318, 2004.
-
(2004)
J. Electrochem. Soc.
, vol.151
-
-
Claeys, C.1
Mercha, A.2
Simoen, E.3
-
8
-
-
0021201529
-
Reliable approach to charge-pumping measurements in mos transistors
-
G. Groeseneken, H. E. Maes, N. Beltrán, and R. F. De Keersmaecker, "A reliable approach to charge-pumping measurements in MOS transistors," IEEE Trans. Electron Devices, vol. ED-31, no. 1, pp. 42-53, Jan. 1984. (Pubitemid 14561846)
-
(1984)
IEEE Transactions on Electron Devices
, vol.ED-31
, Issue.1
, pp. 42-53
-
-
Groeseneken Guido1
Maes Herman, E.2
Beltran Nicolas3
De Keersmaecker, R.F.4
-
9
-
-
0033882264
-
A new charge-pumping technique for profiling the interface-state and oxide-trapped charges in MOSFET's
-
Feb.
-
Y.-L. Chu, D.-W. Lin, and C.-Y. Wu, "A new charge-pumping technique for profiling the interface-state and oxide-trapped charges in MOSFET's," IEEE Trans. Electron Devices, vol. 47, no. 2, pp. 348-353, Feb. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, Issue.2
, pp. 348-353
-
-
Chu, Y.-L.1
Lin, D.-W.2
Wu, C.-Y.3
-
10
-
-
0033743361
-
Flicker noise in deep submicron nMOS transistors
-
N. Lukyanchikova, N. Garbar, M. Petrichuk, E. Simoen, and C. Claeys, "Flicker noise in deep submicron nMOS transistors," Solid State Electron., vol. 44, pp. 1239-1245, 2000.
-
(2000)
Solid State Electron.
, vol.44
, pp. 1239-1245
-
-
Lukyanchikova, N.1
Garbar, N.2
Petrichuk, M.3
Simoen, E.4
Claeys, C.5
-
11
-
-
0035366684
-
Improved analysis of low frequency noise in dynamic threshold MOS/SOI transistors
-
DOI 10.1016/S0026-2714(01)00021-X, PII S002627140100021X
-
S. Haendler, J. Jomaah, G. Ghibaudo, and F. Balestra, "Improved analysis of low frequency noise in dynamic threshold MOS/SOI transistors," Microelectron. Rel., vol. 41, pp. 855-860, 2001. (Pubitemid 32536026)
-
(2001)
Microelectronics and Reliability
, vol.41
, Issue.6
, pp. 855-860
-
-
Haendler, S.1
Jomaah, J.2
Ghibaudo, G.3
Balestra, F.4
-
12
-
-
1442311895
-
Low frequency noise and hot-carrier reliability in advanced SOI MOSFETs
-
F. Dieudonné, S. Haendler, J. Jomaah, and F. Balestra, "Low frequency noise and hot-carrier reliability in advanced SOI MOSFETs," Solid State Electron., vol. 48, pp. 985-997, 2004.
-
(2004)
Solid State Electron.
, vol.48
, pp. 985-997
-
-
Dieudonné, F.1
Haendler, S.2
Jomaah, J.3
Balestra, F.4
-
13
-
-
33846592716
-
Low-frequency noise in silicon-on-insulator devices and technologies
-
E.Simoen,A.Mercha,C.Claeys, and N. Lukyanchikova, "Low-frequency noise in silicon-on-insulator devices and technologies," Solid State Electron., vol. 51, pp. 16-37, 2007.
-
(2007)
Solid State Electron.
, vol.51
, pp. 16-37
-
-
Simoena, E.1
Mercha, A.2
Claeys, C.3
Lukyanchikova, N.4
-
14
-
-
0025398785
-
Unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors
-
DOI 10.1109/16.47770
-
K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, "A unified model for the flicker noise in metal-oxide semiconductor field-effect transistors," IEEE Trans. Electron Devices, vol. 37, no. 3, pp. 654-665, Mar. 1990. (Pubitemid 20699942)
-
(1990)
IEEE Transactions on Electron Devices
, vol.37
, Issue.3 PART 1
, pp. 654-665
-
-
Hung Kwok, K.1
Ko Ping, K.2
Hu Chenming3
Cheng Yiu, C.4
-
15
-
-
49949124297
-
Low frequency noise in MOS transistors-I Theory
-
S. Christensson, I. Lundstrom, and C. Svensson, "Low frequency noise in MOS transistors-I Theory," Solid State Electron., vol. 11, pp. 797-812, 1968.
-
(1968)
Solid State Electron.
, vol.11
, pp. 797-812
-
-
Christensson, S.1
Lundstrom, I.2
Svensson, C.3
-
16
-
-
0024732795
-
1/f noise technique to extract the oxide trap density near the conduction band edge of silicon
-
DOI 10.1109/16.34242
-
R. Jayaraman and C. G. Sodini, "A 1/f noise technique to extract the oxide trap density near the conduction band edge of silicon," IEEE Trans. Electron Devices, vol. 36, no. 9, pp. 1773-1782, Sep. 1989. (Pubitemid 20617806)
-
(1989)
IEEE Transactions on Electron Devices
, vol.36
, Issue.9 PART 1
, pp. 1773-1782
-
-
Jayaraman Raj1
Sodini Charles, G.2
-
17
-
-
14844296459
-
2 gate stack n-MOSFETs
-
DOI 10.1016/j.sse.2004.08.021, PII S0038110105000377, 5th International Workshop on the Ultimate Intergration of Silicon, ULIS 2004
-
2 gate stack n-MOSFETs," Solid State Electron., vol. 49, pp. 702-707, 2005. (Pubitemid 40340017)
-
(2005)
Solid-State Electronics
, vol.49
, Issue.5
, pp. 702-707
-
-
Simoen, E.1
Mercha, A.2
Pantisano, L.3
Claeys, C.4
Young, E.5
-
18
-
-
33749072883
-
Size-dependent effects on electrical contacts to nanotubes and nanowires
-
Jul.
-
F. Léonard and A. A. Talin, "Size-dependent effects on electrical contacts to nanotubes and nanowires," Phys. Rev. Lett., vol. 97, 026804, Jul. 2006.
-
(2006)
Phys. Rev. Lett.
, vol.97
, pp. 026804
-
-
Léonard, F.1
Talin, A.A.2
-
19
-
-
40049092325
-
Fringingfield effects on electrical resistivity of semiconductor nanowire-metal contacts
-
J.Hu,Y. Liu,C.Z. Ning, R.Dutton, and S.-M. Kang, "Fringingfield effects on electrical resistivity of semiconductor nanowire-metal contacts," Appl. Phys. Lett., vol. 92, 083503, 2008.
-
(2008)
Appl. Phys. Lett.
, vol.92
, pp. 083503
-
-
Hu, J.1
Liu, Y.2
Ning, C.Z.3
Dutton, R.4
Kang, S.-M.5
-
20
-
-
77949384348
-
Characteristics of the extracted from Si-nanowire FETs using the Y-function technique
-
R. H. Baek, C. K. Baek, S. W. Jung, Y. Y. Yeoh, D.-W. Kim, J.-S. Lee, D. M. Kim, and Y. H. Jeong, "Characteristics of the extracted from Si-nanowire FETs using the Y-function technique," IEEE Trans. Nanotech-nol., vol. 9, no. 2, pp. 212-217, 2010.
-
(2010)
IEEE Trans. Nanotech-nol.
, vol.9
, Issue.2
, pp. 212-217
-
-
Baek, R.H.1
Baek, C.K.2
Jung, S.W.3
Yeoh, Y.Y.4
Kim, D.-W.5
Lee, J.-S.6
Kim, D.M.7
Jeong, Y.H.8
-
22
-
-
64549154802
-
Random telegraph noise in n-type and p-type silicon nanowire transistors
-
S. Yang, K. H. Yeo, D.-W. Kim, K.-I. Seo, D. Park, G. Y. Jin, K. S. Oh, and H. Shin, "Random telegraph noise in n-type and p-type silicon nanowire transistors," in IEDM Tech. Dig., 2008, pp. 765-768.
-
(2008)
IEDM Tech. Dig.
, pp. 765-768
-
-
Yang, S.1
Yeo, K.H.2
Kim, D.-W.3
Seo, K.-I.4
Park, D.5
Jin, G.Y.6
Oh, K.S.7
Shin, H.8
-
23
-
-
23344447576
-
Explicit continuous model for long-channel undoped surrounding gate MOSFETs
-
DOI 10.1109/TED.2005.852892
-
B. Iñ́ýguez, D. Jiménez, J. Roig, H. A. Hamid, L. F. Marsal, and J. Pallarès, "Explicit continuous model for long-channel undoped surrounding gate MOSFETs," IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 1868-1873, Aug. 2005. (Pubitemid 41100652)
-
(2005)
IEEE Transactions on Electron Devices
, vol.52
, Issue.8
, pp. 1868-1873
-
-
Iniguez, B.1
Jimenez, D.2
Roig, J.3
Hamid, H.A.4
Marsal, L.F.5
Pallares, J.6
-
24
-
-
70449088986
-
Investigation on hot carrier reliability of gate-all-around twin Si nanowire field effect yTransistor
-
Y. Y. Yeoh, S. D. Suk, K. H. Yeo, D.-W. Kim, G. Y. Jin, and K. S. Oh, "Investigation on hot carrier reliability of gate-all-around twin Si nanowire field effect yTransistor," in Proc. IEEE Int. Rel. Phys. Symp., 2009, pp. 400-404.
-
(2009)
Proc. IEEE Int. Rel. Phys. Symp.
, pp. 400-404
-
-
Yeoh, Y.Y.1
Suk, S.D.2
Yeo, K.H.3
Kim, D.-W.4
Jin, G.Y.5
Oh, K.S.6
|