-
1
-
-
79955523137
-
-
International Technology Roadmap for Semiconductors 2006 [Online]. Available:
-
International Technology Roadmap for Semiconductors 2006 [Online]. Available: http://public.itrs.net/
-
-
-
-
3
-
-
4544255406
-
A 0.6-1.2 V low-power configurable PLL architecture for 6 GHz-300 MHz applications in a 90 nmCMOS process
-
Jun.
-
P. Raha, A 0.6-1.2 V low-power configurable PLL architecture for 6 GHz-300 MHz applications in a 90 nmCMOS process, in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2004, 232-235.
-
(2004)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 232-235
-
-
Raha, P.1
-
4
-
-
70349246574
-
An interpolating digitally controlled oscillator for a wide-range all-digital PLL
-
Sep.
-
K.-H. Choi, J.-B. Shin, J.-Y. Sim, H.-J. Park, An interpolating digitally controlled oscillator for a wide-range all-digital PLL, IEEE Trans. Circuits Syst. I, Reg. Papers. 56, 9, 2055-2063, Sep. 2009.
-
(2009)
IEEE Trans. Circuits Syst. I, Reg. Papers.
, vol.56
, Issue.9
, pp. 2055-2063
-
-
Choi, K.-H.1
Shin, J.-B.2
Sim, J.-Y.3
Park, H.-J.4
-
5
-
-
67649262209
-
∞ compensation
-
May
-
∞ compensation, IEEE Trans. Circuits Syst. I, Reg. Papers. 56, 5, 865-876, May 2009.
-
(2009)
IEEE Trans. Circuits Syst. I, Reg. Papers.
, vol.56
, Issue.5
, pp. 865-876
-
-
Kim, J.Y.1
Yao, C.-W.2
Willson Jr., A.N.3
-
6
-
-
61349151852
-
A 5-GHz CMOS frequency synthesizer with an injection-locked frequency divider and differential switched capacitors
-
Feb.
-
P.-Y. Deng and J.-F. Kiang, A 5-GHz CMOS frequency synthesizer with an injection-locked frequency divider and differential switched capacitors, IEEE Trans. Circuits Syst. I, Reg. Papers. 56, 2, 320-326, Feb. 2009.
-
(2009)
IEEE Trans. Circuits Syst. I, Reg. Papers.
, vol.56
, Issue.2
, pp. 320-326
-
-
Deng, P.-Y.1
Kiang, J.-F.2
-
8
-
-
39749108910
-
A 0.5-V 1.9-GIk low-power phase-locked loop in 0.18-μm CMOS
-
DOI 10.1109/VLSIC.2007.4342699, 4342699, 2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
-
∞ CMOS, in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2007, 164-165. (Pubitemid 351306607)
-
(2007)
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
, pp. 164-165
-
-
Hsieh, H.-H.1
Lu, C.-T.2
Lu, L.-H.3
-
9
-
-
77951022665
-
A low-power quadrature VCO and its application to a 0.6-V 2.4-GHz PLL
-
Apr.
-
C.-T. Lu, H.-H. Hsieh, L.-H. Lu, A low-power quadrature VCO and its application to a 0.6-V 2.4-GHz PLL, IEEE Trans. Circuits Syst. I, Reg. Papers. 57, 4, 793-802, Apr. 2010.
-
(2010)
IEEE Trans. Circuits Syst. I, Reg. Papers.
, vol.57
, Issue.4
, pp. 793-802
-
-
Lu, C.-T.1
Hsieh, H.-H.2
Lu, L.-H.3
-
10
-
-
41549143170
-
A design method and developments of a low-power and high-resolution multiphase generation system
-
Apr.
-
A. Matsumoto, S. Sakiyama, Y. Tokunaga, T. Morie, S. Dosho, A design method and developments of a low-power and high-resolution multiphase generation system, IEEE J. Solid-State Circuits. 43, 831-843, Apr. 2008.
-
(2008)
IEEE J. Solid-State Circuits.
, vol.43
, pp. 831-843
-
-
Matsumoto, A.1
Sakiyama, S.2
Tokunaga, Y.3
Morie, T.4
Dosho, S.5
-
11
-
-
29044434691
-
A 0.94-ps-RMS-jitter 0.016-mm 2.5-GHz multiphase generator PLL with 360 digitally programmable phase shifter for 10-Gb/s Serial links
-
Dec.
-
T. Toifl et al., A 0.94-ps-RMS-jitter 0.016-mm 2.5-GHz multiphase generator PLL with 360 digitally programmable phase shifter for 10-Gb/s Serial links, IEEE J. Solid-State Circuit. 40, 12, 2700-2712, Dec. 2005.
-
(2005)
IEEE J. Solid-State Circuit.
, vol.40
, Issue.12
, pp. 2700-2712
-
-
Toifl, T.1
-
12
-
-
33745157914
-
TH transistors by Analog T- Switch (AT-Switch) and super cut-off CMOS
-
DOI 10.1109/VLSIC.2005.1469348, 1469348, 2005 Symposium on VLSI Circuits - Digest of Technical Papers
-
TH transistors by analog T-switch (AT-switch) and super cut-off CMOS, in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2005, 122-125. (Pubitemid 43898003)
-
(2005)
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
, vol.2005
, pp. 122-125
-
-
Ishida, K.1
Kanda, K.2
Tamtrakarn, A.3
Kawaguchi, H.4
Sakurai, T.5
-
13
-
-
3843092731
-
A 10-b 150-MSample/s 1.8-V 123-mW CMOS A/D converter with 400-MHz input bandwidth
-
Aug.
-
J.-B. Park, S.-M. Yoo, S.-W. Kim, Y.-J. Cho, S.-H. Lee, A 10-b 150-MSample/s 1.8-V 123-mW CMOS A/D converter with 400-MHz input bandwidth, IEEE J. Solid-State Circuits. 39, 1335-1337, Aug. 2004.
-
(2004)
IEEE J. Solid-State Circuits.
, vol.39
, pp. 1335-1337
-
-
Park, J.-B.1
Yoo, S.-M.2
Kim, S.-W.3
Cho, Y.-J.4
Lee, S.-H.5
-
14
-
-
29044442913
-
0.5-V analog circuit techniques and their application in OTA and filter design
-
DOI 10.1109/JSSC.2005.856280
-
S. Chatterjee, Y. Tsividis, P. R. Kinget, 0.5-V analog circuit techniques and their application in OTA and filter design, IEEE J. Solid- State Circuits. 40, 2373-2387, Dec. 2005. (Pubitemid 41789134)
-
(2005)
IEEE Journal of Solid-State Circuits
, vol.40
, Issue.12
, pp. 2373-2387
-
-
Chatterjee, S.1
Tsividis, Y.2
Kinget, P.3
-
15
-
-
67349134725
-
Designing an ultralow- voltage phase-locked loop using a bulk-driven technique
-
May
-
Y.-L. Lo, W.-B. Yang, T.-S. Chao, K.-H. Cheng, Designing an ultralow- voltage phase-locked loop using a bulk-driven technique, IEEE Trans. Circuits Syst. II, Exp. Briefs. 56, 5, 339-343, May 2009.
-
(2009)
IEEE Trans. Circuits Syst. II, Exp. Briefs.
, vol.56
, Issue.5
, pp. 339-343
-
-
Lo, Y.-L.1
Yang, W.-B.2
Chao, T.-S.3
Cheng, K.-H.4
-
16
-
-
0024091885
-
A variable delay line PLL for CPUcoprocessor synchronization
-
May
-
M. G. Johnson and E. L. Hudson, A variable delay line PLL for CPUcoprocessor synchronization, IEEE J. Solid-State Circuits. 23, 1218-1223, May 1988.
-
(1988)
IEEE J. Solid-State Circuits.
, vol.23
, pp. 1218-1223
-
-
Johnson, M.G.1
Hudson, E.L.2
-
17
-
-
0030291248
-
A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for microprocessor clock generation
-
PII S001892009608095X
-
V. von Kaenel, D. Aebischer, C. Piguet, E. Dijkstra, A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for microprocessor clock generation, IEEE J. Solid-State Circuits. 31, 1715-1722, Nov. 1996. (Pubitemid 126580888)
-
(1996)
IEEE Journal of Solid-State Circuits
, vol.31
, Issue.11
, pp. 1715-1722
-
-
Von Kaenel, V.1
Aebischer, D.2
Piguet, C.3
Dijkstra, E.4
-
21
-
-
0030290680
-
Low-jitter process-independent DLL and PLL based on self-biased techniques
-
PII S0018920096079462
-
J. G. Maneatis, Low-jitter process-independent DLL and PLL based on self-biased techniques, IEEE J. Solid-State Circuits. 35, 1723-1732, Nov. 1996. (Pubitemid 126580889)
-
(1996)
IEEE Journal of Solid-State Circuits
, vol.31
, Issue.11
, pp. 1723-1732
-
-
Maneatis, J.G.1
-
22
-
-
0034248698
-
A low-noise fast-lock phase-locked loop with adaptive bandwidth control
-
Aug.
-
J. Lee and B. Kim, A low-noise fast-lock phase-locked loop with adaptive bandwidth control, IEEE J. Solid-State Circuits. 35, 1137-1145, Aug. 2000.
-
(2000)
IEEE J. Solid-State Circuits.
, vol.35
, pp. 1137-1145
-
-
Lee, J.1
Kim, B.2
-
23
-
-
0034296002
-
A low-jitter mixed-mode DLL for high-speed DRAM applications
-
Oct.
-
J. J. Kim, S.-B. Lee, T.-S. Jung, C.-H. Kim, S.-I. Cho, B. Kim, A low-jitter mixed-mode DLL for high-speed DRAM applications, IEEE J. Solid-State Circuits. 35, 1430-1436, Oct. 2000.
-
(2000)
IEEE J. Solid-State Circuits.
, vol.35
, pp. 1430-1436
-
-
Kim, J.J.1
Lee, S.-B.2
Jung, T.-S.3
Kim, C.-H.4
Cho, S.-I.5
Kim, B.6
-
24
-
-
0038150591
-
Performance characteristics of an ultra-low power VCO
-
May
-
M. J. Deen, M. H. Kazemeini, S. Naseh, Performance characteristics of an ultra-low power VCO, in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2003, 697-700.
-
(2003)
Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS)
, pp. 697-700
-
-
Deen, M.J.1
Kazemeini, M.H.2
Naseh, S.3
-
25
-
-
4644285938
-
New current-mode wave-pipelined architectures for high-speed analog-to-digital converters
-
Jan.
-
C.-Y. Wu and Y.-Y. Liow, New current-mode wave-pipelined architectures for high-speed analog-to-digital converters, IEEE Trans. Circuits Syst. I, Reg. Papers. 51, 1, 25-37, Jan. 2004.
-
(2004)
IEEE Trans. Circuits Syst. I, Reg. Papers.
, vol.51
, Issue.1
, pp. 25-37
-
-
Wu, C.-Y.1
Liow, Y.-Y.2
-
28
-
-
0032671890
-
A 1.6-GHz dual modulus prescaler using the extended true-single-phase- clock CMOS circuit technique(TSPC)
-
Jan.
-
J. N. Soares, Jr and W. A. M. V. Noije, A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique(TSPC), IEEE J. Solid-State Circuits. 34, 97-102, Jan. 1999.
-
(1999)
IEEE J. Solid-State Circuits.
, vol.34
, pp. 97-102
-
-
Soares Jr., J.N.1
Noije, W.A.M.V.2
-
31
-
-
16244416575
-
Ultra-low-voltage high-performance CMOS VCOs using transformer feedback
-
DOI 10.1109/JSSC.2005.843614
-
K. Kwok and H. C. Luong, Ultra-low-voltage high-performance CMOS VCOs using transformer feedback, IEEE J. Solid-State Circuits. 40, 652-660, Mar. 2005. (Pubitemid 40448821)
-
(2005)
IEEE Journal of Solid-State Circuits
, vol.40
, Issue.3
, pp. 652-660
-
-
Kwok, K.1
Luong, H.C.2
-
32
-
-
34247616142
-
A low voltage and power LC VCO implemented with dynamic threshold voltage MOSFETS
-
DOI 10.1109/LMWC.2007.895720
-
S.-L. Jang and C.-F. Lee, A low voltage and power LC VCO implemented with dynamic threshold voltage MOSFETS, IEEE Microw. Wireless Compon. Lett. 17, 5, 376-378, May 2007. (Pubitemid 46685726)
-
(2007)
IEEE Microwave and Wireless Components Letters
, vol.17
, Issue.5
, pp. 376-378
-
-
Jang, S.-L.1
Lee, C.-F.2
-
33
-
-
28144442261
-
∞ SOI CMOS
-
Feb.
-
∞ SOI CMOS, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2005, 416-417.
-
(2005)
IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers
, pp. 416-417
-
-
Kim, J.1
Plouchart, J.-O.2
Zamdmer, N.3
Trzcinski, R.4
Wu, K.5
Gross, B.J.6
Kim, M.7
-
34
-
-
33947655416
-
An on-chip calibration technique for reducing supply voltage sensitivity in ring oscillators
-
DOI 10.1109/JSSC.2007.892194
-
T. Wu, K. Mayaram, U.-K. Moon, An on-chip calibration technique for reducing supply voltage sensitivity in ring oscillators, IEEE J. Solid-State Circuits. 42, 775-783, Apr. 2007. (Pubitemid 46495393)
-
(2007)
IEEE Journal of Solid-State Circuits
, vol.42
, Issue.4
, pp. 775-783
-
-
Wu, T.1
Mayaram, K.2
Moon, U.-K.3
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