An on-chip calibration technique for reducing supply voltage sensitivity in ring oscillators

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 4, 2007, Pages 775-783

  Wu, Ting ^a,b   Mayaram, Kartikeya ^a,b   Moon, Un Ku ^a,b  

^a IEEE   (United States)

^b Oregon State University   (United States)

Author keywords

Digital calibration; Phase locked loop; Supply voltage sensitivity; Voltage controlled oscillator

Indexed keywords

DIGITAL CALIBRATION; ON-CHIP CALIBRATION; SUPPLY VOLTAGE SENSITIVITY;

ELECTRIC POWER UTILIZATION; JITTER; MICROPROCESSOR CHIPS; ROBUSTNESS (CONTROL SYSTEMS); SPURIOUS SIGNAL NOISE; VOLTAGE CONTROL;

VARIABLE FREQUENCY OSCILLATORS;

EID: 33947655416     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.892194     Document Type: Article

References (11)

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