A compact, low-power low-jitter digital PLL

European Solid-State Circuits Conference

Volumn , Issue , 2003, Pages 101-104

  Fahim, Am M ^a  

^a QUALCOMM INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE BANDWIDTH CONTROL; ALL DIGITAL; CHARGE-PUMP; CMOS TECHNOLOGY; DIGITAL PLL; LOOP BANDWIDTH; LOOP FILTER; LOW-POWER CONSUMPTION;

CMOS INTEGRATED CIRCUITS; PHASE LOCKED LOOPS;

JITTER;

EID: 33846224141     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2003.1257082     Document Type: Conference Paper

References (6)

1. I. Hwang, et. al, "A Digitally Controlled Phase-Locked Loop with a Digital Phase-Frequency Detector for Fast Acquisition, " IEEE JSSC, Oct. 2001, vol. 36, pp. 1574-1581.
2. C. Chung, C. Lee, "An All-Digital Phase-Locked Loop for High-Speed Clock Generation, " IEEE JSSC, Feb 2003, vol. 38, pp. 347-351.
3. A. Bellaouar and M. Elmasry, Low-Power Digital VLSI Design, Boston: Kluwer Academic Publishers, 1995.
4. Tien-Yu, W. et. al., "A Low Glitch 10-bit 75MHz CMOS Video D/A Converter, " IEEE JSSC, vol. Jan. 1995, pp. 68-72.
5. Maneatis, J., "Low-jitter and process independent DLL and PLL based on self biased techniques, " ISSCC, 1996, pp. 130-131.
6. Ahn, H. and Allstot, D., "A low-jitter 1. 9-V CMOS PLL for UltraSPARC microprocessor applications, " IEEE JSSC, vol. 35, Mar 2000, pp. 450-454.