-
1
-
-
0346342381
-
A 40-Gb/s clock and data recovery circuit in 0.18-μm CMOS technology
-
Dec.
-
J. Lee and B. Razavi, "A 40-Gb/s clock and data recovery circuit in 0.18-μm CMOS technology," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2181-2190, Dec. 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.12
, pp. 2181-2190
-
-
Lee, J.1
Razavi, B.2
-
2
-
-
16544371955
-
A 27-mW 3.6 Gb/s I/O transceiver
-
Apr.
-
K.-L. Wong, H. Hatamkhani, M. Mansuri, and C.-K. Ken Yang, "A 27-mW 3.6 Gb/s I/O transceiver," IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 602-612, Apr. 2004.
-
(2004)
IEEE J. Solid-State Circuits
, vol.39
, Issue.4
, pp. 602-612
-
-
Wong, K.-L.1
Hatamkhani, H.2
Mansuri, M.3
Ken Yang, C.-K.4
-
3
-
-
0031276490
-
A semi-digital dual delay-locked loop
-
Nov.
-
S. Sidkopoulos and M. Horowitz, "A semi-digital dual delay-locked loop," IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 1683-1692, Nov. 1997.
-
(1997)
IEEE J. Solid-State Circuits
, vol.32
, Issue.11
, pp. 1683-1692
-
-
Sidkopoulos, S.1
Horowitz, M.2
-
4
-
-
0036857082
-
Adaptive supply serial links with sub-1-V operation and per-pin clock recovery
-
Nov.
-
J. Kim and M. Horowitz, "Adaptive supply serial links with sub-1-V operation and per-pin clock recovery," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1403-1413, Nov. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, Issue.11
, pp. 1403-1413
-
-
Kim, J.1
Horowitz, M.2
-
5
-
-
0034798939
-
An 84-mW 4-Gb/s clock and data recovery circuit for serial link applica-tions
-
Kyoto, Japan, Jun.
-
M.-J. E. Lee, W. Dally, J. Poulton, P. Chiang, and S. Greenwood, "An 84-mW 4-Gb/s clock and data recovery circuit for serial link applica-tions," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Kyoto, Japan, Jun. 2001, pp. 149-152.
-
(2001)
IEEE Symp. VLSI Circuits Dig. Tech. Papers
, pp. 149-152
-
-
Lee, M.-J.E.1
Dally, W.2
Poulton, J.3
Chiang, P.4
Greenwood, S.5
-
6
-
-
0037852911
-
A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs
-
May
-
K. K. Chang, J. Wei, C. Huang, S. Li, K. Donnelly, M. Horowitz, Y. Li, and S. Sidiropoulos, "A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs," IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 747-754, May 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.5
, pp. 747-754
-
-
Chang, K.K.1
Wei, J.2
Huang, C.3
Li, S.4
Donnelly, K.5
Horowitz, M.6
Li, Y.7
Sidiropoulos, S.8
-
7
-
-
11944250423
-
A 160-2550 MHz CMOS active clock deskewing PLL using analog phase interpolation
-
Jan.
-
A. Maxim, "A 160-2550 MHz CMOS active clock deskewing PLL using analog phase interpolation," IEEE J. Solid-State Circuits, vol. 40, no. 1,pp. 110-131, Jan. 2005.
-
(2005)
IEEE J. Solid-State Circuits
, vol.40
, Issue.1
, pp. 110-131
-
-
Maxim, A.1
-
8
-
-
4444270147
-
A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os
-
Sep.
-
R. Farjad-Rad, A. Nguyen, J. M. Tran, T. Greer, J. Poulton, W. J. Dally, J. H. Edmondson, R. Senthinathan, R. Rathi, M.-J. E. Lee, and H.-T. Ng, "A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os," IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1553-1561, Sep. 2004.
-
(2004)
IEEE J. Solid-State Circuits
, vol.39
, Issue.9
, pp. 1553-1561
-
-
Farjad-Rad, R.1
Nguyen, A.2
Tran, J.M.3
Greer, T.4
Poulton, J.5
Dally, W.J.6
Edmondson, J.H.7
Senthinathan, R.8
Rathi, R.9
Lee, M.-J.E.10
Ng, H.-T.11
-
9
-
-
0033280776
-
A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability
-
Dec.
-
P. Larsson, "A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability," IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1951-1960, Dec. 1999.
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, Issue.12
, pp. 1951-1960
-
-
Larsson, P.1
-
10
-
-
0036858189
-
Jitter optimization based on phase-locked loop design parameters
-
Nov.
-
M. Mansuri and C.-K. K. Yang, "Jitter optimization based on phase-locked loop design parameters," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1375-1382, Nov. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, Issue.11
, pp. 1375-1382
-
-
Mansuri, M.1
Yang, C.-K.K.2
-
11
-
-
0019079092
-
Charge-pump phase-lock loops
-
Nov.
-
F. Gardner, "Charge-pump phase-lock loops," IEEE Trans. Commun., vol. COM-28, no. 11, pp. 1849-1858, Nov. 1980.
-
(1980)
IEEE Trans. Commun.
, vol.COM-28
, Issue.11
, pp. 1849-1858
-
-
Gardner, F.1
-
12
-
-
0024104186
-
Z-domain model for discrete-time PLL's
-
Nov.
-
J. Hein and J. Scott, "z-domain model for discrete-time PLL's, " IEEE Trans. Circuits Syst., vol. 35, no. 11, pp. 1393-1400, Nov. 1988.
-
(1988)
IEEE Trans. Circuits Syst.
, vol.35
, Issue.11
, pp. 1393-1400
-
-
Hein, J.1
Scott, J.2
-
13
-
-
0031165398
-
Jitter in ring oscillators
-
Jun.
-
J. McNeill, "Jitter in ring oscillators," IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 870-879, Jun. 1997.
-
(1997)
IEEE J. Solid-State Circuits
, vol.32
, Issue.6
, pp. 870-879
-
-
McNeill, J.1
-
14
-
-
0035368885
-
A 1.25-GHz 0.35 μm monolithic CMOS PLL based on a multiphase ring oscillator
-
Jun.
-
L. Sun and T. Kwasniewski, "A 1.25-GHz 0.35 μm monolithic CMOS PLL based on a multiphase ring oscillator," IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 910-916, Jun. 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, Issue.6
, pp. 910-916
-
-
Sun, L.1
Kwasniewski, T.2
|