A 0.5-V 1.9-GIk low-power phase-locked loop in 0.18-μm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 164-165

  Hsieh, Hsieh Hung ^a   Lu, Chung Ting ^a   Lu, Liang Hung ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; PHASE LOCKED LOOPS; THRESHOLD VOLTAGE;

FORWARD BODY BIAS TECHNIQUE; SUPPLY VOLTAGE;

CMOS INTEGRATED CIRCUITS;

EID: 39749108910     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342699     Document Type: Conference Paper

References (3)

1. B. Razavi, Design of Integrated Circuits for Optical Communications. New York: McGraw-Hill, 2002.
2. W. Rhee, "Design of high-performance CMOS charge pumps in phase-locked loops," IEEE International Symposium on Circuits and Systems, vol. 2, pp. 545-548, June 1999.
3. H.-H. Hsieh and L.-H. Lu, "A high-performance CMOS voltage-controlled oscillator for ultra-low-voltage operations," to appear in IEEE Trans, on Microwave Theory and Techniques.