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Volumn 35, Issue 10, 2000, Pages 1430-1436

Low-jitter mixed-mode DLL for high-speed DRAM applications

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DELAY CIRCUITS; DIGITAL CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC CONVERTERS; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC WAVEFORMS; TRANSFER FUNCTIONS;

EID: 0034296002     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.871319     Document Type: Article
Times cited : (41)

References (9)
  • 1
    • 0030290680 scopus 로고    scopus 로고
    • Low-jitter and process-independent DLL and PLL based on self-biased techniques
    • Nov.
    • J. G. Maneatis, "Low-jitter and process-independent DLL and PLL based on self-biased techniques," IEEE J. Solid-State Circuits, vol. 31, pp. 1728-1732, Nov. 1998.
    • (1998) IEEE J. Solid-State Circuits , vol.31 , pp. 1728-1732
    • Maneatis, J.G.1
  • 2
    • 0032206426 scopus 로고    scopus 로고
    • A 640 MB/s bi-directional data strobed, double-data-rate SDRAM with a 40-mW DLL circuit for a 256-Mb memory system
    • Nov.
    • C. Kim et al., "A 640 MB/s bi-directional data strobed, double-data-rate SDRAM with a 40-mW DLL circuit for a 256-Mb memory system," IEEE J. Solid-State Circuits, vol. 31, pp. 1703-1710, Nov. 1998.
    • (1998) IEEE J. Solid-State Circuits , vol.31 , pp. 1703-1710
    • Kim, C.1
  • 3
    • 0033097302 scopus 로고    scopus 로고
    • A direct-skew-detect synchronous mirror delay for application-specific integrated circuits
    • Mar.
    • T. Saeki et al., "A direct-skew-detect synchronous mirror delay for application-specific integrated circuits," IEEE J. Solid-State Circuits, vol. 34, pp. 372-379, Mar. 1999.
    • (1999) IEEE J. Solid-State Circuits , vol.34 , pp. 372-379
    • Saeki, T.1
  • 4
    • 0030168989 scopus 로고    scopus 로고
    • Digital delay locked loop and design technique for high-speed synchronous interface
    • June
    • Y. Okajima et al., "Digital delay locked loop and design technique for high-speed synchronous interface," IEICE Trans. Electron., vol. E79-C, June 1996.
    • (1996) IEICE Trans. Electron. , vol.E79-C
    • Okajima, Y.1
  • 5
    • 0033221599 scopus 로고    scopus 로고
    • A 2.5-V, 333-Mb/s/pin, 1-Gb, double-data-rate synchronous DRAM
    • Nov.
    • H. Yoon et al., "A 2.5-V, 333-Mb/s/pin, 1-Gb, double-data-rate synchronous DRAM," IEEE J. Solid-State Circuits, vol. 34, pp. 1589-1599, Nov. 1999.
    • (1999) IEEE J. Solid-State Circuits , vol.34 , pp. 1589-1599
    • Yoon, H.1
  • 6
    • 0030123564 scopus 로고    scopus 로고
    • A 250-622-MHz deskew and jitter-suppressed clock buffer using two-loop architecture
    • Apr.
    • S. Tanoi et al., "A 250-622-MHz deskew and jitter-suppressed clock buffer using two-loop architecture," IEEE J. Solid-State Circuits, vol. 31, pp. 487-493, Apr. 1996.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , pp. 487-493
    • Tanoi, S.1
  • 8
    • 0032624146 scopus 로고    scopus 로고
    • A low-noise 900-MHz VCO in 0.6-μm CMOS
    • May
    • C.-H. Park and B. Kim, "A low-noise 900-MHz VCO in 0.6-μm CMOS," IEEE J. Solid-State Circuits, vol. 34, pp. 586-591, May 1999.
    • (1999) IEEE J. Solid-State Circuits , vol.34 , pp. 586-591
    • Park, C.-H.1    Kim, B.2
  • 9
    • 0342377541 scopus 로고    scopus 로고
    • A low-jitter mixed DLL for high-speed DRAMs
    • Duisburg, Germany, Sept.
    • J. J. Kim and B. Kim, "A low-jitter mixed DLL for high-speed DRAMs," in Proc. 25th Eur. Solid-State Circuits Conf., Duisburg, Germany, Sept. 1999, pp. 134-137.
    • (1999) Proc. 25th Eur. Solid-State Circuits Conf. , pp. 134-137
    • Kim, J.J.1    Kim, B.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.