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Volumn 43, Issue 4, 2008, Pages 831-842

A design method and developments of a low-power and high-resolution multiphase generation system

Author keywords

Coupled ring oscillator; Level shifter; Multiphase; Phase locked loop (PLL)

Indexed keywords

ELECTRIC CONNECTORS; ELECTRIC CURRENTS; MOBILE PHONES; MOS DEVICES; PHASE LOCKED LOOPS; TOPOLOGY; VIDEODISKS;

EID: 41549143170     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.917567     Document Type: Conference Paper
Times cited : (31)

References (10)
  • 2
    • 0027851095 scopus 로고
    • Precise delay generation using coupled oscillators
    • Dec
    • J. G. Maneatis and M. A. Horowitz, "Precise delay generation using coupled oscillators," IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1273-1282, Dec. 1993.
    • (1993) IEEE J. Solid-State Circuits , vol.28 , Issue.12 , pp. 1273-1282
    • Maneatis, J.G.1    Horowitz, M.A.2
  • 3
    • 0035368885 scopus 로고    scopus 로고
    • A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator
    • Jun
    • L. Sun and T. A. Kwansniewski, "A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator," IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 910-916, Jun. 2001.
    • (2001) IEEE J. Solid-State Circuits , vol.36 , Issue.6 , pp. 910-916
    • Sun, L.1    Kwansniewski, T.A.2
  • 4
    • 0036857082 scopus 로고    scopus 로고
    • Adaptive supply serial links with sub-1 -V operation and per-pin clock recovery
    • Nov
    • J. Kim and M. A. Horowitz, "Adaptive supply serial links with sub-1 -V operation and per-pin clock recovery," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1403-1413, Nov. 2002.
    • (2002) IEEE J. Solid-State Circuits , vol.37 , Issue.11 , pp. 1403-1413
    • Kim, J.1    Horowitz, M.A.2
  • 9
    • 33646513900 scopus 로고    scopus 로고
    • Phase averaging and interpolation using resistor strings or resistor rings for multi-phase clock generation
    • May
    • J.-M. Chou, Y.-T. Hsieh, and J.-T. Wu, "Phase averaging and interpolation using resistor strings or resistor rings for multi-phase clock generation," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 5, pp. 984-991, May 2006.
    • (2006) IEEE Trans. Circuits Syst. I, Reg. Papers , vol.53 , Issue.5 , pp. 984-991
    • Chou, J.-M.1    Hsieh, Y.-T.2    Wu, J.-T.3
  • 10
    • 34548855024 scopus 로고    scopus 로고
    • A 40-to-800 MHz locking multi-phase DLL
    • Y.-S. Kim et al., "A 40-to-800 MHz locking multi-phase DLL," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 306-307.
    • (2007) IEEE ISSCC Dig. Tech. Papers , pp. 306-307
    • Kim, Y.-S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.