-
1
-
-
28144462887
-
A CMOS 1×-to 16 ×-speed DVD write channel IC
-
Y. Konno, K. Tomioka, Y. Aiba, K. Yamazoe, and B.-S. Song, "A CMOS 1×-to 16 ×-speed DVD write channel IC," in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 568-569.
-
(2005)
IEEE ISSCC Dig. Tech. Papers
, pp. 568-569
-
-
Konno, Y.1
Tomioka, K.2
Aiba, Y.3
Yamazoe, K.4
Song, B.-S.5
-
2
-
-
0027851095
-
Precise delay generation using coupled oscillators
-
Dec
-
J. G. Maneatis and M. A. Horowitz, "Precise delay generation using coupled oscillators," IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1273-1282, Dec. 1993.
-
(1993)
IEEE J. Solid-State Circuits
, vol.28
, Issue.12
, pp. 1273-1282
-
-
Maneatis, J.G.1
Horowitz, M.A.2
-
3
-
-
0035368885
-
A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator
-
Jun
-
L. Sun and T. A. Kwansniewski, "A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator," IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 910-916, Jun. 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, Issue.6
, pp. 910-916
-
-
Sun, L.1
Kwansniewski, T.A.2
-
4
-
-
0036857082
-
Adaptive supply serial links with sub-1 -V operation and per-pin clock recovery
-
Nov
-
J. Kim and M. A. Horowitz, "Adaptive supply serial links with sub-1 -V operation and per-pin clock recovery," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1403-1413, Nov. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, Issue.11
, pp. 1403-1413
-
-
Kim, J.1
Horowitz, M.A.2
-
5
-
-
33745155097
-
A 4.0 GHz 0.18 μm CMOS PLL based on an interpolative oscillator
-
F. H. Gebara, J. D. Schaub, A. J. Drake, K. J. Nowka, and R. B. Brown, "A 4.0 GHz 0.18 μm CMOS PLL based on an interpolative oscillator," in Symp. VLSI Circuits Dig. Tech. Papers, 2005, pp. 100-103.
-
(2005)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 100-103
-
-
Gebara, F.H.1
Schaub, J.D.2
Drake, A.J.3
Nowka, K.J.4
Brown, R.B.5
-
6
-
-
39749126969
-
A PLL for a DVD x 16 write system with 63 output phases and 32 ps resolution
-
S. Dosho, S. Sakiyama, N. Takeda, Y. Tokunaga, and T. Morie, "A PLL for a DVD x 16 write system with 63 output phases and 32 ps resolution," in IEEE ISSCC Dig. Tech. Papers, 2006, pp. 2422-2423.
-
(2006)
IEEE ISSCC Dig. Tech. Papers
, pp. 2422-2423
-
-
Dosho, S.1
Sakiyama, S.2
Takeda, N.3
Tokunaga, Y.4
Morie, T.5
-
7
-
-
39749083469
-
Multiphase-output level shift system used in multiphase PLL for low power application
-
Jun
-
A. Matsumoto, S. Sakiyama, Y. Tokunaga, T. Morie, and S. Dosho, "Multiphase-output level shift system used in multiphase PLL for low power application," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2007, pp. 228-229.
-
(2007)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 228-229
-
-
Matsumoto, A.1
Sakiyama, S.2
Tokunaga, Y.3
Morie, T.4
Dosho, S.5
-
8
-
-
0037630665
-
A 125 MHz 8b digital-to-phase converter
-
J.-M. Chou, Y.-T. Hsieh, and J.-T. Wu, "A 125 MHz 8b digital-to-phase converter," in IEEE ISSCC Dig. Tech. Papers, 2003, pp. 436-437.
-
(2003)
IEEE ISSCC Dig. Tech. Papers
, pp. 436-437
-
-
Chou, J.-M.1
Hsieh, Y.-T.2
Wu, J.-T.3
-
9
-
-
33646513900
-
Phase averaging and interpolation using resistor strings or resistor rings for multi-phase clock generation
-
May
-
J.-M. Chou, Y.-T. Hsieh, and J.-T. Wu, "Phase averaging and interpolation using resistor strings or resistor rings for multi-phase clock generation," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 5, pp. 984-991, May 2006.
-
(2006)
IEEE Trans. Circuits Syst. I, Reg. Papers
, vol.53
, Issue.5
, pp. 984-991
-
-
Chou, J.-M.1
Hsieh, Y.-T.2
Wu, J.-T.3
-
10
-
-
34548855024
-
A 40-to-800 MHz locking multi-phase DLL
-
Y.-S. Kim et al., "A 40-to-800 MHz locking multi-phase DLL," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 306-307.
-
(2007)
IEEE ISSCC Dig. Tech. Papers
, pp. 306-307
-
-
Kim, Y.-S.1
|