Low-noise fast-lock phase-locked loop with adaptive bandwidth control

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 8, 2000, Pages 1137-1145

  Lee, Joonsuk ^a,b   Kim, Beomsup ^a  

^a IBM MICROELECTRONICS   (United States)

^b Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE ALGORITHMS; ADAPTIVE CONTROL SYSTEMS; ELECTRIC CURRENTS; FREQUENCY HOPPING; RECURSIVE FUNCTIONS; SPURIOUS SIGNAL NOISE; TRANSFER FUNCTIONS; VARIABLE FREQUENCY OSCILLATORS;

ADAPTIVE BANDWIDTH CONTROL; ANALOG RECURSIVE BANDWIDTH CONTROL ALGORITHM; DUTY CYCLE CORRECTOR; FAST LOCK PHASE LOCKED LOOP; GEAR SHIFTING ALGORITHM; PHASE ERROR;

PHASE LOCKED LOOPS;

EID: 0034248698     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.859502     Document Type: Article

References (13)

1. J. Dunning et al., "An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors," IEEE J. Solid-State Circuits, vol. 30, pp. 412-122, Apr. 1995.
2. B. Kim, D. N. Helman, and P. R. Gray, "A 30-MHz hybrid analog/digital clock recovery circuit in 2-μm CMOS," IEEE J. Sold-State Circuits, vol. 25, pp. 1385-1394, Dec. 1990.
3. M. Mizuno et al., "A 0.18 μm CMOS hot-standby phase-locked loop using a noise immune adaptive-gain voltage-controlled oscillator," ISSCC Dig. Tech. Papers, pp. 268-269, Feb. 1995.
4. G. Roh, Y. Lee, and B. Kim, "An optimum phase-acquisition technique for charge-pump phase-locked loops," IEEE Trans. Circuit Syst. II, vol. 44, pp. 729-740, Sept. 1997.
5. B. Chun, Y. Lee, and B. Kim, "Design of variable loop gain of dual-loop DPLL," IEEE Trans. Commun., vol. 45, pp. 1520-1522, Dec. 1997.
6. P. F. Driessen, "DPLL bit synchronizer with rapid acquisition using adaptive Kalman filtering techniques," IEEE Trans. Commun., vol. 452, pp. 2673-2675, Sept. 1994.
7. B. Kim, "Dual-loop DPLL gear-shifting algorithm for fast synchronization," IEEE Trans. Circuits Syst. II, vol. 44, pp. 577-586, July 1997.
8. S. Haykin, Adaptive Filter Theory. Englewood Cliffs, NJ: Prentice Hall, 1995.
9. T. C. Weigandt, B. Kim, and P. R. Gray, "Analysis of timing jitter in CMOS ring oscillators," in Proc. Int. Symp. Circuit and Systems, vol. 4, London, U.K., June 1994, pp. 27-30.
10. C. H. Park and B. Kim, "A low-noise 900-MHz VCO in 0.6-μm CMOS," IEEE J. Solid-State Circuits, vol. 34, pp. 586-591, May 1999.
11. K. Lim, C. H. Park, and B. Kim, "Low noise clock synthesizer design using optimal bandwidth," in Proc. Int. Symp. Circuit and Systems, Monterey, CA, June 1998, pp. 163-166.
12. J. Lee and B. Kim, "A 250 MHz low jitter adaptive bandwidth PLL," ISSCC Dig. Tech. Papers, pp. 346-347, Feb. 1999.
13. J. McNeil, "Jitter in ring oscillators," IEEE J. Solid-State Circuits, vol. 32, pp. 870-879, June 1997.