Power-driven flip-flop merging and relocation

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2011, Pages 107-114

  Wang, Shao Huan ^a   Liang, Yu Yi ^a   Kuo, Tien Yu ^a   Mak, Wai Kei ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

clock network; low power; multi bit flip flop; post placement

Indexed keywords

CLOCK NETWORK; CLOCK NETWORK SYNTHESIS; CLOCK POWER CONSUMPTION; DENSITY CONSTRAINTS; LOW POWER; MULTI-BITS; POST PLACEMENT; RELOCATION APPROACH; SWITCHING POWER; TIMING DRIVEN PLACEMENT; WIRE LENGTH;

ELECTRIC CLOCKS; MERGING; RELOCATION;

FLIP FLOP CIRCUITS;

EID: 79955107204     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1960397.1960423     Document Type: Conference Paper

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