A new clock mesh buffer sizing methodology for skew and power reduction

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI 2008

Volumn , Issue , 2008, Pages 227-232

  Wilke, Gustavo ^a   Reis, Ricardo ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; ELECTRIC CLOCKS; TECHNOLOGY;

ARRIVAL TIME; ARRIVAL TIMES; CLOCK NETWORKS; CLOCK SIGNALLING; CLOCK SKEWS; POWER CONSUMPTION; POWER REDUCTIONS; PROPAGATION DELAYS; SIZING ALGORITHMS; VLSI TECHNOLOGIES;

MESH GENERATION;

EID: 51849165585     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2008.91     Document Type: Conference Paper

References (11)

1. G. Geannopoulos and X. Dai, "An adaptative digital deskewing circuit for clock distribution networks," in Proceedings of the IEEE Internaional Solid State Circuits Conference (ISSCC'98), 1998, pp. 400-401.
2. S. Tam et al., "Clock generation and distribution for the first ia-64 microprocessor," IEEE Journal of Solid-State Circuits, vol. 35, no. 11, pp. 1545-1552, Nov 2000.
3. G. Venkataraman et al., "Practical techniques to reduce skew and its variations in buffered clock networks," in International Conference on Computer-Aided Design, November 2005, pp. 592-596.
4. T. Xanthopoulos et al., "The design and analysis of the clock distribution network for a 1.2ghz alpha microprocessor," in Proceedings of the IEEE Internaional Solid State Circuits Conference (ISSCC'01), February 2001, pp. 402-403.
5. P. Restle et al., "The clock distribution of the power4 microprocessor," in Proceedings of the IEEE Internaional Solid State Circuits Conference (ISSCC'02), February 2002, pp. 144-145.
6. J. M. Hart et al., "Implementation of a fourth-generation 1.8ghz dual-core sparc v9 microprocessor," IEEE Journal of Solid-State Circuits, vol. 41, no. 1, pp. 210-217, Jan 2006.
7. M. G. R. Thomson, P. J. Restle, and N. K. James, "A 5ghz duty-cycle correcting clock distribution network for the power6 microprocessor," in Proceedings of the IEEE In-ternaional Solid State Circuits Conference (ISSCC'06), Feb 2006, pp. 1522-1529.
8. Cadence, SoC Encounter User Guide: Product Version 5.2, Dec. 2005.
9. G. Venkataraman et al., "Combinatorial algorithms for fast clock mesh optimization," in ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design. New York, NY, USA: ACM, 2006, pp. 563-567.
10. C.-Y. Yeh et al., "Clock distribution architectures: A comparative study." in ISQED. IEEE Computer Society, 2006, pp. 85-91.
11. V. Mehrotra and D. Boning, "Technology scaling impact of variation on clock skew and interconnect delay," in Interconnect Technology Conference, 2001. Proceedings of the IEEE 2001 International, June 2001, pp. 122-124.