Low power clock gates optimization for clock tree distribution

Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010

Volumn , Issue , 2010, Pages 488-492

  Teng, Siong Kiong ^a   Soin, Norhayati ^b  

^a Intel Technology Malaysia Sdn Bhd   (Malaysia)

^b UNIVERSITY OF MALAYA   (Malaysia)

Author keywords

Clock gating; Clock tree synthesis; Low power

Indexed keywords

CLOCK BUFFER; CLOCK GATING; CLOCK GATING TECHNIQUES; CLOCK TREE; CLOCK TREE DISTRIBUTION; CLOCK TREE SYNTHESIS; DYNAMIC POWER; GATE LOCATION; INDUSTRIAL DESIGN; LOW POWER; LOW POWER CLOCK; LOW-POWER DIGITAL CIRCUITS; MERGING ALGORITHMS; MULTIPLE LEVELS; OPTIMIZATION TECHNIQUES; SINGLE LEVEL; SPLITTING AND MERGING;

ALGORITHMS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CLOCKS; MERGING; MICROPROCESSOR CHIPS; OPTIMIZATION; PRODUCT DESIGN; SYNTHESIS (CHEMICAL);

TREES (MATHEMATICS);

EID: 77952606758     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2010.5450528     Document Type: Conference Paper

References (12)

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