Low power low leakage clock gated static pulsed flip-flop

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 3658-3661

  Seyedi, A S ^a   Rasouli, S H ^a   Amirabadi, A ^a   Afzali Kusha, A ^a  

^a UNIVERSITY OF TEHRAN   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; ELECTRIC POWER UTILIZATION; LEAKAGE CURRENTS; LOGIC GATES; TIMING CIRCUITS;

CLOCK GATING; CLOCK PULSE GENERATORS; DYNAMIC POWER CONSUMPTION;

FLIP FLOP CIRCUITS;

EID: 34547311979     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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