SCOPUS 정보 검색 플랫폼

ITC 2010 - 2010 International Conference on Recent Trends in Information, Telecommunication, and Computing

Volumn , Issue , 2010, Pages 253-256

Design of a low power flip-flop using CMOS deep submicron technology

(2) Naik, Surya a,b Chandel, Rajeevan a

a NATIONAL INSTITUTE OF TECHNOLOGY (India)

b LINGAYA'S UNIVERSITY (India)

Author keywords

CMOS; Delay; Figure of merit; Leakage current; Power; TSPC flip flop

Indexed keywords

CLOCKING SYSTEMS; CMOS; DEEP SUB-MICRON TECHNOLOGY; FIGURE OF MERIT; HIGH SPEED DESIGNS; LEAKAGE POWER; LOW POWER; M-TECHNOLOGIES; POWER CONSUMPTION; POWER DISSIPATION; PROPAGATION DELAYS; RUNTIMES; SHORT PULSE; SPICE SIMULATIONS; TRUE-SINGLE-PHASE-CLOCKING;

CMOS INTEGRATED CIRCUITS; LEAKAGE CURRENTS; SPICE; TRANSISTORS;

FLIP FLOP CIRCUITS;

EID: 77953096718 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/ITC.2010.100 Document Type: Conference Paper

Times cited : (9)

References (9)

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9
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.