Buffer sizing for clock power minimization subject to general skew constraints

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 159-164

  Wang, Kai ^a   Marek Sadowska, Malgorzata ^a  

^a University of California   (United States)

Author keywords

Clock skew scheduling; Sequential linear programming; Sizing

Indexed keywords

ALGORITHMS; ELECTRIC POWER SYSTEMS; ENERGY DISSIPATION; LINEAR PROGRAMMING; OPTIMIZATION; VOLTAGE MEASUREMENT;

CLOCK SKEW SCHEDULING; POWER SUPPLY VOLTAGE; PROBLEM FORMULATION; VOLTAGE DROP;

ELECTRIC CLOCKS;

EID: 4444373753     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996614     Document Type: Conference Paper

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