Automatic feedback control of shared hybrid caches in 3D chip multiprocessors

Proceedings - 19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011

Volumn , Issue , 2011, Pages 393-400

  Sharifi, Akbar ^a   Kandemir, Mahmut ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; APPLICATION-LEVEL PERFORMANCE; AUTOMATIC FEEDBACK; CACHE ARCHITECTURE; CHIP MULTIPROCESSOR; EXPERIMENTAL EVALUATION; IN-CHIP; L2 CACHE; MAGNETIC RAMS; PERFORMANCE TARGETS; PHASE-CHANGE RAM; POWER CONSUMPTION; PROCESSING CORE; RUNNING APPLICATIONS; SHARED CACHE; TIME INTERVAL; TWO LAYERS;

CACHE MEMORY; FEEDBACK CONTROL; MULTIPROCESSING SYSTEMS; NETWORK ARCHITECTURE; THREE DIMENSIONAL;

MICROPROCESSOR CHIPS;

EID: 79955047392     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PDP.2011.83     Document Type: Conference Paper

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