Pseudo-circuit: Accelerating communication for on-chip interconnection networks

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2010, Pages 399-408

  Ahn, Minseon ^a   Kim, Eun Jung ^a  

^a Texas AandM University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AVERAGE ENERGY; CHIP MULTIPROCESSOR; COMMUNICATION LATENCY; COMMUNICATION PARADIGM; COMMUNICATION PATTERN; COMMUNICATION PERFORMANCE; CYCLE ACCURATE; DE FACTO; EVALUATION RESULTS; HARDWARE COST; NAS PARALLEL BENCHMARKS; NETWORK COMMUNICATIONS; NETWORK SIMULATORS; NUMBER OF HOPS; ON-CHIP INTERCONNECTION NETWORK; PACKET-SWITCHED; PARTIAL CIRCUITS; PERFORMANCE IMPROVEMENTS; ROUTER ARCHITECTURE; SINGLE CHIPS; SYNTHETIC WORKLOADS; TEMPORAL LOCALITY;

ARTS COMPUTING; COMMUNICATION; COMPUTER ARCHITECTURE; ENERGY UTILIZATION; INTERCONNECTION NETWORKS; NETWORK PERFORMANCE; PACKET NETWORKS; PROGRAM PROCESSORS; ROUTERS; SWITCHING CIRCUITS;

NETWORK ARCHITECTURE;

EID: 79951685103     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2010.10     Document Type: Conference Paper

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