An accurate model for soft error rate estimation considering dynamic voltage and frequency scaling effects

Microelectronics Reliability

Volumn 51, Issue 2, 2011, Pages 460-467

  Firouzi, Farshad ^a   Salehi, Mostafa E ^a   Wang, Fan ^b   Fakhraie, Sied Mehdi ^a  

^a UNIVERSITY OF TEHRAN   (Iran)

^b JUNIPER NETWORKS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCURATE FORMULAS; ANALYTIC MODELING; BENCHMARK CIRCUIT; CHIP DESIGNERS; CRITICAL CHALLENGES; DYNAMIC SCALING; DYNAMIC VOLTAGE; DYNAMIC VOLTAGE AND FREQUENCY SCALING; FABRICATION TECHNOLOGIES; FAULT RATES; FAULT TOLERANT SYSTEMS; FAULT-TOLERANT; FREQUENCY ADJUSTMENT; LOW-POWER SYSTEMS; MAXIMUM EFFICIENCY; OPERATING FREQUENCY; POWER CONSUMPTION; POWER MANAGEMENT SCHEME; RE-CONFIGURABLE; RELIABILITY MODEL; RUNTIMES; SHRINKING FEATURE SIZES; SILICON INTEGRATED CIRCUITS; SINGLE CHIPS; SOFT ERROR; SOFT ERROR RATE; SOFT ERROR RATE ESTIMATIONS; SUPPLY VOLTAGES; TRANSISTOR COUNT;

DESIGN; ENERGY MANAGEMENT; ESTIMATION; FREQUENCY ESTIMATION; ONLINE SYSTEMS;

RELIABILITY;

EID: 79551494251     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2010.08.016     Document Type: Conference Paper

References (58)

1. Zhang Y, Chakrabarty K, Swaminathan. Energy-aware fault tolerance in fixed-priority real-time embedded systems. In: Proceedings of the international conference on computer aided design; 2003. p. 209.
2. Azizi O, Mahesri A, Lee BC, Patel SJ, Horowitz M. Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis. In: Proceedings of the international symposium on computer architecture; 2010. p. 26-36.
3. S. Kaxiras, and M. Martonosi Computer architecture techniques for power-efficiency 2008 Morgan and Claypool Publishers
4. Zhu D, Melhem R, Mosse D. The effects of energy management on reliability in real-time embedded systems. In: Proceedings of the international conference on computer aided design; 2004. p. 35-40.
5. S. Yang, W. Wang, T. Lu, W. Wolf, N. Vijaykrishnan, and Y. Xie Case study of reliability-aware and low-power design IEEE Trans Very Large Scale Integr (VLSI) Syst 16 7 2008 861 873
6. J.F. Ziegler Terrestrial cosmic ray intensities IBM J Res Dev 42 1 1998 117 139
7. M.B. Tahooria, B. Mullinsa, and D.R. Kaelia Obtaining FPGA soft error next term rate in high performance information systems Microelectron Reliab 49 5 2009 551 557
8. S.Z. Shazlia, and M.B. Tahooria Using Boolean satisfiability for computing soft error next term rates in early design stages Microelectron Reliab 50 1 2010 149 159
9. Ejlali A, Schmitz MT, Al-Hashimi BM, Miremadi SG, Rosinger P. Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy. In: Proceedings of the international symposium on low power electronic design; 2005. p. 281-6.
10. Zhang Y, Chakrabarty K. Energy-aware adaptive check pointing in embedded real-time systems. In: Proceedings of design and automation in europe; 2003. p. 918-23.
11. Zhu D. Reliability-aware dynamic energy management in dependable embedded real-time systems. In: Proceedings of RTAS; 2006. p. 397-407.
12. A. Ejlali, B.M. Al-Hashimi, M.T. Schmitz, P. Rosinger, and S.G. Miremadi Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems IEEE Trans Very Large Scale Integr (VLSI) Syst 14 4 2006 323 335
13. Dabiri F, et al. Reliability-aware optimization for DVS-enabled real-time embedded systems. In: Proceedings of ISQED; 2008. p. 780-783.
14. T. Nguyen, Yoad Yagil, Norbert Seifert, and Mike Reitsma Chip level soft error estimation method IEEE Trans Dev Mater Reliab 5 3 2005 365 380
15. Ramakrishnan K, Rajaraman R, Suresh S, Vijaykrishnan N, Xie Y, Irwin MJ. Variation impact on SER of combinational circuits. In: Proceedings of the international symposium on quality electronic design; 2007. p. 911-6.
16. P. Hazucha, C. Svensson, and S.A. Wender Cosmic-ray soft error rate characterization of a standard 0.6-m CMOS process IEEE J Solid-State Circ 35 10 2000 1422 1429
17. Cha H, Patel JH. A Logic-level model for alpha-particle hits in CMOS circuits. In: Proceedings of IEEE international conference on computer design; 1993. p. 538-42.
18. Nguyen HT, Yagil Y. A Systematic approach to SER estimation and solutions. In: Proceedings of IEEE international symposium on reliability physics; 2003. p. 60-70.
19. Wang F, Agrawal VD. Soft error rate determination for nanoscale sequential logic. In: Proceedings of the international symposium on quality electronic design; 2009. p. 225-30.
20. Nanoscale integration and modeling (NIMO) Group at Arizona State University, the Predictive Technology Model (PTM). < http://ptm.asu.edu/ > [retrieved 11.06.10].
21. S. Buchner, M. Baze, D. Brown, D. McMorrow, and J. Melinger Comparison of error rates in combinational and sequential logic IEEE Trans Nucl Sci 44 6 1997 2209 2216
22. Hass KJ, Gambles JW, Walker B, Zampaglione M. Mitigating single event upsets from combinational logic. In: Proceedings of the 7th NASA symposium on VLSI design; 1998. p. 411-9.
23. N. Seifert, and N. Tam Timing vulnerability factors of sequentials IEEE Trans Dev Mater Reliab 4 3 2004 516 522
24. Shivakumar P, Kistler M, Keckler SW, Burger D, Alvisi L. Modeling the effect of technology trends on the soft error rate of combinational logic. In: Proceedings of the international conference on dependable systems and networks; 2002. p. 389-98.
25. Gill B, Seifert N, Zia V. Comparison of Alpha-particle and neutron-induced combinational and sequential logic error rates at the 32 nm technology node. In: Proceedings of IEEE int reliability physics symposium; 2009. p. 199-205.
26. TM microprocessor. In: Proceedings of IEEE international symposium on reliability physics, May 2001. p. 259-65.
27. J.L. Leray Effects of atmospheric neutrons on devices, at sea level and in avionics embedded systems Microelectron Reliab 47 5 2007 1827 1835
28. T.F. Irom, and F.F. Farmanesh Frequency dependence of single-event upset in advanced commercial PowerPC microprocessors IEEE Trans Nucl Sci 51 6 2004 3505 3509
29. Degalahal V, Ramanarayanan R, Vijaykrishnan N, Xie Y, Irwin MJ. The effect of threshold voltages on the soft error rate. In: Proceedings of the 5th international symposium quality electronic design (ISQED); 2004. p. 503-8.
30. S.V. Walstra, and C. Dai Circuit-level modeling of soft errors in integrated circuits IEEE Trans Dev Mater Reliab 5 3 2005 358 364
31. Firouzi F, Salehi ME, Wang F, Fakhraie SM, Safari S. Reliability-aware dynamic voltage and frequency scaling. In: IEEE computer society annual symposium on VLSI; 2010.
32. Firouzi F. Fault tolerant design methods for network processors at various abstraction levels in nano-scale CMOS implementation technologies. MSc thesis, ECE, at University of Tehran, Iran; 2010.
33. T. Sakurai, and A.R. Newton Alpha-power law MOSFET model and its applications to CMOS inverter IEEE J Solid-State Circ 25 2 1990 584 594
34. K.A. Bowman, and B.L. Austin A physical alpha-power law MOSFET model IEEE J Solid-State Circ 34 1999 1410 1414
35. R. Gonzalez Supply and threshold voltage scaling for low power CMOS IEEE J Solid-State Circ 32 1997 1210 1216
36. Wang F, Agrawal VD. Soft error rates with inertial and logical masking. In: Proceedings of IEEE international conference on VLSI design, January 2009. p. 459-64.
37. Wang F, Agrawal VD. Soft error rate determination for nanometer CMOS VLSI circuits. In: Proceedings of IEEE Southeastern symposium on system theory, March 16-18, TA-3.5; 2008. p. 324-8.
38. Wang, F, Agrawal VD. Soft error determination for nanoscale sequential logic. In: Proceedings of the 11th international symposium on quality electronic design (ISQED'2010), March 2010. p. 225-30.
39. Balaji Narasimham On-chip characterization of single-event transient pulse widths IEEE Trans Dev Mater Reliab 6 4 2004 2506 2511
40. Balaji Narasimham Characterization of neutron- and alpha-particle-induced transients leading to soft errors in 90-nm CMOS technology IEEE Trans Dev Mater Reliab 9 2 2009 325 333
41. R. Baumann Soft errors in advanced computer systems IEEE Des Test Comput 22 3 2005 258 266
42. Rajaraman Ramanarayanan On modeling soft errors at the device and logic levels for combinational circuits IEEE Trans Dependable Secure Comput 6 3 2009 202 216
43. Baumann R. The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction. In: International electron devices meeting digest; 2002. p. 329-32.
44. Matthew J. Gadlage Assessing alpha particle-induced single event transient vulnerability in a 90-nm CMOS technology IEEE Electron Dev Lett 29 6 2008 638 641
45. Measurement and reporting of alpha particles and terrestrial cosmic ray-induced soft errors in semiconductor devices, JEDEC Standard JESD89A, October 2007.
46. Rao RR, Chopra K, Blaauw D, Sylvester D. An efficient static algorithm for computing the soft error rates of combinational circuits. In: Proceedings of the conference on design, automation and test in Europe; 2006. p. 164-9.
47. Rajaraman R, Kim JS, Vijaykrishnan N, Xie Y, Irwin MJ. SEAT-LA: a soft error analysis tool for combinational logic. In: Proceedings of the 19th international conference VLSI design; 2006. p. 499-502.
48. Asadi G, Tahoori MB. An accurate ser estimation method based on propagation probability. In: Proc design automation and test in europe conference; 2005. p. 306-7.
49. G.C. Messenger Collection of charge on junction nodes from ion tracks IEEE Trans Nucl Sci 29 6 1982 2024 2031
50. P. Hazucha, and C. Svensson Impact of CMOS technology scaling on the atmospheric neutron soft error rate IEEE Trans Nucl Sci 47 6 2000 2586 2594
51. Ness D, Lilja D. Guiding circuit level fault-tolerance design with statistical methods. In: Proceedings of the design, automation, test Europe (DATE); 2008. p. 348-53.
52. G.C. Messenger, and M. Ash Single event phenomena 1997 Chapman & Hall
53. M.S. Gordon Measurement of the flux and energy spectrum of cosmic-ray induced neutrons on the ground IEEE Trans Nucl Sci 51 6 2004 3427 3434
54. Hass KJ, Ambles JW. Single event transients in deep submicron CMOS. In: Proceedings of Midwest symposium on circuits and systems; 1999. p. 122-5.
55. G.R. Srinivasan Modelling the cosmic ray-induced soft-error rate in integrated circuits: an overview Microelectron Reliab 37 4 1997 691
56. Balaji Narasimham Characterization of digital single event transient pulse-widths in 130-nm and 90-nm CMOS technologies IEEE Trans Nucl Sci 54 6 2007 2506 2511
57. Seifert N, Slankard P, Kirsch M, Narasimham B, Zia V, Brookreson C, et al. Radiation-induced soft error rates of advanced CMOS bulk devices. In: Proceedings of the IEEE international physics symposium; 2006. p. 217-25.
58. P. Hazucha, and C. Svensson Modeling and simulation of single-event effects in digital devices and ICs IEEE Trans Nucl Sci 47 6 2008 1854 1878