Design and optimization of power-gated circuits with autonomous data retention

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 2, 2011, Pages 227-236

  Seomun, Jun ^a   Shin, Youngsoo ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Application specific integrated circuit (ASIC); data retention; leakage; low power; power gating

Indexed keywords

CIRCUIT STATE; CONTROL SIGNAL; DATA RETENTION; DESIGN AND OPTIMIZATION; FAST CHARGES; IN-CONTROL; LEAKAGE; LOW POWER; OPTIMIZATION PROCEDURES; POWER GATINGS; POWER MANAGEMENT UNIT; PULSE WIDTH; SHORT PULSE; STANDBY MODE; SUB-THRESHOLD LEAKAGE; WIRE LENGTH; WIRING CONGESTION;

ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC RESISTANCE MEASUREMENT; ENERGY DISSIPATION; ENERGY MANAGEMENT; INTEGRATED CIRCUITS; LEAKAGE CURRENTS; NANOTECHNOLOGY; OPTIMIZATION; SEMICONDUCTOR SWITCHES; SWITCHING CIRCUITS;

DATA REDUCTION;

EID: 79151471282     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2033356     Document Type: Article

References (24)

1. J. Friedrich, B. McCredie, N. James, B. Huott, B. Curran, E. Fluhr, E. Chan, G. Mittal, D. Plass, Y. Chan, S. Chu, H. Le, L. Clark, J. Ripley, S. Taylor, J. Dilullo, and M. Lanzerotti, "Design of the Power6 microprocessor", in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2007, pp. 96-97.
2. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits, "Proc. IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003.
3. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "A 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS", IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 847-854, Aug. 1995.
4. K. Usami, N. Kawabe, M. Koizumi, K. Seta, and T. Furusawa, "Automated selective multi-threshold design for ultra-low standby applications", in Proc. Int. Symp. Low Power Electron. Des., Aug. 2002, pp. 202-206.
5. S. G. Narendra and A. Chandrakasan, Eds., Leakage in Nanometer CMOS Technologies. New York: Springer, 2005.
6. M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low Power Methodology Manual for System-on-Chip Design. New York: Springer, 2007.
7. S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada, "A 1-V high-speed MTCMOS circuit scheme for power-down application circuits", IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 861-869, Jun. 1997.
8. J. Kao and A. Chandrakasan, "MTCMOS sequential circuits", in Proc. Eur. Solid-State Circuits Conf., Sep. 2001, pp. 317-320.
9. V. Zyuban and S. V. Kosonocky, "Low power integrated scan-retention mechanism", in Proc. Int. Symp. Low Power Electron. Des., Aug. 2002, pp. 98-102.
10. H.-S. Won, K.-S. Kim, K.-O. Jeong, K.-T. Park, K.-M. Choi, and J.-T. Kong, "An MTCMOS design methodology and its application to mobile computing", in Proc. Int. Symp. Low Power Electron. Des., Aug. 2003, pp. 110-115.
11. S. Gururajarao, H. Mair, D. Scott, and U. Ko, "Ultra low area overhead retention flip-flop for power-down applications", U. S. Appl. Pub. 20060267654, Nov. 2006.
12. T. Lueftner, J. Berthold, C. Pacha, G. Georgakos, G. Sauzon, O. Hoemke, J. Beshenar, P. Mahrla, K. Just, P. Hober, S. Henzler, D. S. Landsiedel, A. Yakovleff, A. Klein, R. J. Knight, P. Acharya, A. Bonnardot, S. Buch, and M. Sauer, "A 90-nm CMOS low-power GSM/EDGE multimedia-enhanced baseband processor with 380-MHz ARM926 core and mixed-signal extensions", IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 134-144, Jan. 2007.
13. H. Mair, A. Wang, G. Gammie, D. Scott, P. Royannez, S. Gururajarao, M. Chau, R. Lagerquist, L. Ho, M. Basude, N. Culp, A. Sadate, D. Wilson, F. Dahan, J. Song, B. Carlson, and U. Ko, "A 65-nm mobile multimedia applications processor with an adaptive power management scheme to compensate for variations", in Proc. Symp. VLSI Circuits, Jun. 2007, pp. 224-225.
14. Y. Shin, S. Heo, H.-O. Kim, and J. Choi, "Supply switching with ground collapse: Simultaneous control of subthreshold and gate leakage current in nanometer-scale CMOS circuits", IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 15, no. 7, pp. 758-766, Jul. 2007.
15. H.-O. Kim and Y. Shin, "Semicustom design methodology of power gated circuits for low leakage applications", IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 6, pp. 512-516, Jun. 2007.
16. K. Kumagai, H. Iwaki, H. Yoshida, H. Suzuki, T. Yamada, and S. Kurosawa, "A novel powering-down scheme for low Vt CMOS circuits", in Proc. Symp. VLSI Circuits, Jun. 1998, pp. 44-45.
17. S. Henzler, G. Georgakos, M. Eireiner, T. Nirschl, C. Pacha, J. Berthold, and D. Schmitt-Landsiedel, "Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead", IEEE J. Solid-State Circuits, vol. 41, no. 7, pp. 1654-1661, Jul. 2006.
18. S. Mutoh, S. Shigematsu, Y. Gotoh, and S. Konaka, "Design method of MTCMOS power switch for low-voltage high-speed LSIs", in Proc. Asia South Pac. Des. Autom. Conf., Jan. 1999, pp. 113-116.
19. Synopsys, Mountain View, CA, "Astro user guide", 2006.
20. Opencores, Dobrova, Slovenia, "Projects", 2009. [Online]. Available: http://www.opencores.org/
21. C. Tsui, J. Monteiro, M. Pedram, S. Devadas, A. M. Despain, and B. Lin, "Power estimation methods for sequential logic circuits", IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 3, no. 3, pp. 404-416, Sep. 1995.
22. L. Benini and G. D. Micheli, "State assignment for low power dissipation", IEEE J. Solid-State Circuits, vol. 30, no. 2, pp. 258-268, Mar. 1995.
23. S. Ercolani, M. Favalli, M. Damiani, P. Olivo, and B. Riccó, "Estimate of signal probability in combinational logic networks", in Proc. Eur. Test Conf., Apr. 1989, pp. 132-138.
24. Synopsys, Mountain View, CA, "Design compiler user guide", 2007.