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Volumn , Issue , 2010, Pages 77-84

Aging analysis at gate and macro cell level

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN;

EID: 78650924021     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2010.5654309     Document Type: Conference Paper
Times cited : (46)

References (22)
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    • Reliability simulation in integrated circuit design
    • Cadence Design Systems, Inc., Tech. Rep.
    • "Reliability simulation in integrated circuit design," white paper, Cadence Design Systems, Inc., Tech. Rep., 2003.
    • (2003) White Paper
  • 15
    • 34047187067 scopus 로고    scopus 로고
    • Temporal performance degradation under NBTI: Estimation and design for improved reliability of nanoscale circuits
    • Los Alamitos, CA, USA: IEEE Computer Society
    • B. C. Paul, K. Kang, H. Kufluoglu, M. Alam, and K. Roy, "Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits," in Design, Automation and Test in Europe (DATE), vol. 1. Los Alamitos, CA, USA: IEEE Computer Society, 2006, pp. 169-174.
    • (2006) Design, Automation and Test in Europe (DATE) , vol.1 , pp. 169-174
    • Paul, B.C.1    Kang, K.2    Kufluoglu, H.3    Alam, M.4    Roy, K.5
  • 16
    • 34548312037 scopus 로고    scopus 로고
    • Temperature-aware NBTI modeling and the impact of input vector control on performance degradation
    • San Jose, CA, USA: EDA Consortium
    • Y. Wang, H. Luo, K. He, R. Luo, H. Yang, and Y. Xie, "Temperature- aware NBTI modeling and the impact of input vector control on performance degradation," in Design, Automation and Test in Europe (DATE). San Jose, CA, USA: EDA Consortium, 2007, pp. 546-551.
    • (2007) Design, Automation and Test in Europe (DATE). , pp. 546-551
    • Wang, Y.1    Luo, H.2    He, K.3    Luo, R.4    Yang, H.5    Xie, Y.6
  • 17
    • 37849033240 scopus 로고    scopus 로고
    • A novel gate-level NBTI delay degradation model with stacking effect
    • ser. Lecture Notes in Computer Science, N. Azemard and L. Svensson, Eds. Springer Berlin / Heidelberg
    • H. Luo, Y. Wang, K. He, R. Luo, H. Yang, and Y. Xie, "A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect," in Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, ser. Lecture Notes in Computer Science, N. Azemard and L. Svensson, Eds. Springer Berlin / Heidelberg, 2007, vol. 4644, pp. 160-170.
    • (2007) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation , vol.4644 , pp. 160-170
    • Luo, H.1    Wang, Y.2    He, K.3    Luo, R.4    Yang, H.5    Xie, Y.6
  • 18
    • 0028711580 scopus 로고
    • A survey of power estimation techniques in VLSI circuits
    • Dec.
    • F. N. Najm, "A Survey of Power Estimation Techniques in VLSI Circuits," IEEE Transactions on VLSI Systems, vol. 2, no. 4, pp. 446 - 455, Dec. 1994.
    • (1994) IEEE Transactions on VLSI Systems , vol.2 , Issue.4 , pp. 446-455
    • Najm, F.N.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.