GLACIER: A hot carrier gate level circuit characterization and simulation system for VLSI design

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2000-January, Issue , 2000, Pages 73-79

  Wu, Lifeng ^a   Fang, Jingkun ^a   Yonezawa, Hirokazu ^b   Kawakami, Yoshiyuki ^b   Iwanishi, Nobufusa ^b   Yan, Heting ^a   Chen, Ping ^a   Chen, Alvin I Hsien ^a   Koike, Norio ^b   Okamoto, Yoshifumi ^b   Yeh, Chune Sin ^a   Liu, Zhihong ^a  

^a BTA Technology Inc   (United States)

^b PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; HOT CARRIERS; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT MANUFACTURE; VLSI CIRCUITS;

DEEP SUB-MICRON; GATE LEVEL SIMULATION; GATE-LEVEL CIRCUITS; HOT CARRIER DEGRADATION; MODELING TECHNIQUE; RELIABILITY SIMULATION; SIMULATION SYSTEMS; TRANSISTOR LEVEL;

CIRCUIT SIMULATION;

EID: 0003894724     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2000.838857     Document Type: Conference Paper

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