A novel gate-level NBTI delay degradation model with stacking effect

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4644 LNCS, Issue , 2007, Pages 160-170

  Luo, Hong ^a   Wang, Yu ^a   He, Ku ^a   Luo, Rong ^a   Yang, Huazhong ^a   Xie, Yuan ^b  

^a TSINGHUA UNIVERSITY   (China)

^b PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; NEGATIVE BIAS TEMPERATURE INSTABILITY;

BENCHMARK CIRCUIT; CIRCUIT DEGRADATION; CIRCUIT PERFORMANCE; DEGRADATION MODEL; PERFORMANCE DEGRADATION; PMOS TRANSISTORS; STACKING EFFECT; STRESS VOLTAGES;

DELAY CIRCUITS;

EID: 37849033240     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-74442-9_16     Document Type: Conference Paper

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