Harmonic distortion of unstrained and strained FinFETs operating in saturation

IEEE Transactions on Electron Devices

Volumn 57, Issue 12, 2010, Pages 3303-3311

  Doria, Rodrigo Trevisoli ^a   Cerdeira, Antonio ^b   Martino, Joo Antonio ^a   Simoen, Eddy ^c   Claeys, Cor ^c   Pavanello, Marcelo Antonio ^d  

^a UNIVERSITY OF SÃO PAULO   (Brazil)

^b DEPARTAMENTO DE FÍSICA   (Mexico)

^c IMEC   (Belgium)

^d Faculdade de Engenharia Industrial   (Brazil)

Author keywords

Biaxial strain; distortion; fin shaped field effect transistor (FinFET); silicon on insulator; single transistor amplifier

Indexed keywords

3D DEVICE SIMULATION; BIAXIAL STRAINS; CHANNEL LENGTH; DEVICE CHARACTERIZATION; DISTORTION; FIN WIDTHS; FINFETS; NON-LINEARITY; OPEN-LOOP VOLTAGE; SILICON ON INSULATOR; SINGLE-TRANSISTOR AMPLIFIER; THIRD-ORDER; TRANSISTOR AMPLIFIERS;

AMPLIFIERS (ELECTRONIC); FINS (HEAT EXCHANGE); HARMONIC DISTORTION; INTEGRATED CIRCUITS; THREE DIMENSIONAL;

FIELD EFFECT TRANSISTORS;

EID: 78650021705     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2079936     Document Type: Article

References (34)

1. J. P. Colinge, FinFETs and Other Multi Gate Transistors. New York: Springer-Verlag, 2008.
2. V. Kilchytska, N. Collaert, R. Rooyackers, D. Lederer, J. P. Raskin, and D. Flandre, "Perspective of FinFETs for analog applications," in Proc. ESSDERC, 2004, pp. 65-68.
3. V. Subramanian, B. Parvais, J. Borremans, A. Mercha, D. Linten, P. Wambacq, J. Loo, M. Dehan, C. Gustin, N. Collaert, S. Kubicek, R. Lander, J. Hooker, F. Cubaynes, S. Donnay, M. Jurczak, G. Groeseneken, W. Sansen, and S. Decoutere, "Planar bulk MOSFETs versus FinFETs: An analog/RF perspective," IEEE Trans. Electron Devices, vol. 53, no. 12, pp. 3071-3079, Dec. 2006.
4. A. Kranti, T. M. Chung, D. Flandre, and J. P. Raskin, "Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications," Solid State Electron., vol. 48, no. 6, pp. 947-959, Jun. 2004.
5. 2-TiN gate stack under analog operation," Solid State Electron., vol. 51, no. 2, pp. 285-291, Feb. 2007.
6. B. Hernes and W. Sansen, "Distortion in single-, two-and three-stage amplifiers," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 5, pp. 846-856, May 2005.
7. W. Sansen, "Distortion in elementary transistor circuits," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 3, pp. 315-325, Mar. 1999.
8. P. Wambacq, G. G. E. Gielen, P. R. Kinget, and W. Sansen, "High-frequency distortion analysis of analog integrated circuits," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 3, pp. 335-345, Mar. 1999.
9. V. Subramanian, A. Mercha, B. Parvais, J. Loo, C. Gustin, M. Dehan, N. Collaert, M. Jurczak, G. Groeseneken, W. Sansen, and S. Decoutere, "Impact of fin width on digital and analog performances of n-FinFETs," Solid State Electron., vol. 51, no. 4, pp. 551-559, Apr. 2007.
10. 2 and SiON gate dielectrics and TaN gate electrode," Microelectron. Eng., vol. 80, pp. 386-389, Jun. 2005.
11. C. Gallon, C. Fenouillet-Beranger, S. Denorme, F. Boeuf, V. Fiori, N. Loubet, A. Vandooren, T. Kormann, M. Broekaart, P. Gouraud, F. Leverd, G. Imbert, C. Chaton, C. Laviron, L. Gabette, F. Vigilant, P. Garnier, H. Bernard, A. Tarnowka, R. Pantel, F. Pionnier, S. Jullian, S. Cristoloveanu, and T. Skotnicki, "Mechanical and electrical analysis of strained liner effect in 35 nm fully depleted silicon-on-insulator devices with ultra fin silicon channels," Jpn. J. Appl. Phys., vol. 45, no. 4B, pp. 3058-3063, Apr. 2006.
12. T. Mizuno, N. Sugiyama, T. Tezuka, T. Numata, and S. Takagi, "High-performance strained-SOI CMOS devices using thin film SiGe-on-insulator technology," IEEE Trans. Electron Devices, vol. 50, no. 4, pp. 988-994, Apr. 2003.
13. E. Augendre, G. Eneman, A. De Keersgieter, V. Simons, I. De Wolf, J. Ramos, S. Brus, B. Pawlak, S. Seven, F. Leys, E. Sleeckx, S. Locorotondo, M. Ercken, J.-F. de Marneffe, L. Fei, M. Seacrist, B. Kellerman, M. Goodwin, K. De Meyer, M. Jurczak, and S. Biesemans, "On the scalability of source/drain current enhancement in thin film sSOI," in Proc. ESSDERC, 2005, pp. 301-304.
14. A. Cerdeira, M. A. Alemán, M. Estrada, and D. Flandre, "Integral Function Method for determination of nonlinear harmonic distortion," Solid State Electron., vol. 48, no. 12, pp. 2225-2234, Dec. 2004.
15. N. Collaert, R. Rooyackers, F. Clemente, P. Zimmerman, I. Cayrefoureq, B. Ghyselen, K. T. San, B. Eyckens, M. Jurezak, and S. Biesemans, "Performance enhancement of MUGFET devices using super critical strained-SOI (SC-SSOI) and CESL," in VLSI Symp. Tech. Dig., 2006, pp. 52-53.
16. A. Dixit, A. Kottantharayil, N. Collaert, M. Goodwin, M. Jurczak, and K. D. Meyer, "Analysis of the parasitic S/D resistance in multiple-gate FETs," IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1132-1140, Jun. 2005.
17. S. Sakurai and M. Ismail, Low-Voltage CMOS Operational Amplifiers Theory, Design and Implementation. Norwell, MA: Kluwer, 1994.
18. D based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA," IEEE J. Solid-State Circuits, vol. 31, no. 9, pp. 1314-1319, Sep. 1996.
19. M. A. Pavanello, J. A. Martino, E. Simoen, R. Rooyackers, N. Collaert, and C. Claeys, "Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs," Solid State Electron., vol. 52, no. 12, pp. 1904-1909, Dec. 2008.
20. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433-1439, Oct. 1989.
21. E. Simoen, A. Mercha, C. Claeys, and N. Lukyanchikova, "Low-frequency noise in silicon-on-insulator devices and technologies," Solid State Electron., vol. 51, no. 1, pp. 16-37, Jan. 2007.
22. G. Groenewold and W. J. Lubbers, "Systematic distortion analysis for MOSFET integrators with use of a new MOSFET model," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 41, no. 9, pp. 569-580, Sep. 1994.
23. P. K. McLarty, S. Cristoloveanu, O. Faynot, V. Misra, J. R. Hauser, and J. J. Wortman, "A simple parameter extraction method for ultra-fin gate oxide MOSFETs," Solid State Electron., vol. 38, no. 6, pp. 1175-1177, Jun. 1995.
24. J. Chen, E. Sanchez-Sinencio, and J. Silva-Martinez, "Frequency- dependent harmonic-distortion analysis of a linearized cross-coupled CMOS OTA and its application to OTA-C filters," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 3, pp. 499-510, Mar. 2006.
25. R. T. Doria, A. Cerdeira, J. P. Raskin, D. Flandre, and M. A. Pavanello, "Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation," Microelectron. J., vol. 39, no. 12, pp. 1663-1670, Dec. 2008.
26. R. van Langevelde and F. M. Klaassen, "Effect of gate-field dependent mobility degradation on distortion analysis in MOSFETs," IEEE Trans. Electron Devices, vol. 44, no. 11, pp. 2044-2052, Nov. 1997.
27. Atlas User's Manual\Device Simulation Software, Silvaco Int., Santa Clara, CA, 2007.
28. C. Lombardi, S. Manzini, A. Saporito, and M. Vanzi, "A physically based mobility model for numerical simulation of nonplanar devices," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 7, no. 11, pp. 1164-1171, Nov. 1988.
29. K. Ushida and S. Takagi, "Carrier scattering induced by thickness fluctuation of silicon-on insulator film in ultrathin-body metal-oxide- semiconductor field-effect transistors," Appl. Phys. Lett., vol. 82, no. 17, pp. 2916-2918, Apr. 2003.
30. J. Conde, A. Cerdeira, and M. A. Pavanello, "3D triple-gate simulation considering the crystallographic orientations," in Proc. 23rd Symp. Microelectron. Technol. Devices, 2008, pp. 197-201.
31. S. C. Sun and J. D. Plummer, "Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces," IEEE Trans. Electron Devices, vol. ED-27, no. 8, pp. 1497-1508, Aug. 1980.
32. K. Lee, J. S. Choi, S. P. Sim, and S. K. Kim, "Physical understanding of low-field carrier mobility in silicon MOSFET inversion layer," IEEE Trans. Electron Devices, vol. 38, no. 8, pp. 1905-1912, Aug. 1991.
33. O. Bonno, S. Barraud, F. Andrieu, D. Mariolle, F. Rochette, M. Casse, J. M. Hartmann, F. Bertin, and O. Faynot, "High-field electron mobility in biaxially-tensile strained SOI: Low temperature measurement and correlation with the surface morphology," in VLSI Symp. Tech. Dig., Kyoto, Japan, 2007, pp. 134-135.
34. Y. H. Xie, G. H. Gilmer, C. Roland, P. J. Silverman, S. K. Buratto, J. Y. Cheng, E. A. Fitzgerald, A. R. Kortan, S. Schuppler, M. A. Marcus, and P. H. Citrin, "Semiconductor surface roughness: Dependence on sign and magnitude of bulk strain," Phys. Rev. Lett., vol. 73, no. 22, pp. 3006-3009, Nov. 1994