3D triple-gate simulation considering the crystallographic orientations

ECS Transactions

Volumn 14, Issue 1, 2008, Pages 197-201

  Conde, Jorge E ^a   Cerdeira, Antonio ^a   Pavanello, Marcelo A ^b  

^a DEPARTAMENTO DE FÍSICA   (Mexico)

^b CENTRO UNIVERSITÁRIO DA FEI   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

CRYSTALLOGRAPHIC ORIENTATIONS; MESH STRUCTURES; MOBILITY VALUES; SERIES RESISTANCES; SIDE-WALLS;

THREE DIMENSIONAL COMPUTER GRAPHICS;

MICROELECTRONICS;

EID: 57749201130     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.2956033     Document Type: Conference Paper

References (8)

1. J. Pierre Colinge, "Multiple-gate Silicon-on-Insulator MOS Transistors" Microelectronics Technology and Devices SBMICRO 2003 p. 2-17.
2. M.A. Pavanello, J.A. Martino, E. Simoen, R. Rooyackers, "Evaluation of triple-gate FinFETs with Si02-HfO2-TiN gate stack under analog operation," Solid-State Electronics 51(2007)285-291.
3. Silvaco, ATLAS, 3D device simulator, Version 5.12.1.R, 2006.
4. Claudio Lombardi, Stefano Manzini, Antonio Saporito and Massino Vanzi, "A Physically Based Mobility Model for Numerical Simulation of Nonplanar Devices", IEEE Transaction CAD, 7 (1988) 1164-1171.
5. Silvaco, DevEdit, 3D device simulator, Version 2.8.5.R.
6. Leland Chang, Meikei leong, Min Yang, "CMOS Circuit Performance Enhancement by Surface Orientation Optimi2ation", IEEE Trans. On Electron Devices 51 (2004) 1621-1627.
7. N. Collaert et al., Symposium on VLSI Technology, pp. 108-109, 2005.
8. Abhisek Dixit, Anil Kottantharayil, Nadine Collaert, "Analysis of the Parasitic S/D Resistance in Multiple-Gate FETs", IEEE Trans. on Electron Devices 52 (2005) 1132-1140.