On the scalability of source/drain current enhancement in thin film sSOI

Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference

Volumn 2005, Issue , 2005, Pages 301-304

  Augendre, E ^a   Eneman, G ^a,b,c   De Keersgieter, A ^a   Simons, V ^a   De Wolf, I ^a   Ramos, J ^a   Brus, S ^a   Pawlak, B ^d   Severi, S ^a,b   Leys, F ^a   Sleeckx, E ^a   Locorotondo, S ^a   Ercken, M ^a   De Marneffe, J F ^a   Fei, L ^e   Seacrist, M ^e   Kellerman, B ^e   Goodwin, M ^f   De Meyer, K ^a,b   Jurczak, M ^a   Biesemans, S ^a   more..

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c FUND FOR SCIENTIFIC RESEARCH   (Belgium)

^d PHILIPS RESEARCH LABORATORIES   (Netherlands)

^e MEMC   (United States)

^f TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; SOLID STATE DEVICES; STRAIN; TENSILE STRENGTH; THIN FILMS;

MESA PATTERNING; STRAINED CONTACT ETCH-STOP LAYERS (SCESL); STRAINED SILICON ON INSULATOR (SSOI);

SILICON ON INSULATOR TECHNOLOGY;

EID: 33751401551     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDER.2005.1546645     Document Type: Conference Paper

References (6)

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2. I. Åberg et al., Proc. VLSI Symp. 2004, pp. 52-53
3. T. Numata et al., IEDM 2004 Tech. Digest, pp. 177-180
4. J. Cai et al., IEDM 2004 Tech. Digest, pp.165-168
5. S. E. Thompson et al., IEDM 2004 Tech. Digest, pp. 221-224
6. S. Pidin et al., IEDM 2004 Tech. Digest, pp. 213-216