Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation

Microelectronics Journal

Volumn 39, Issue 12, 2008, Pages 1663-1670

  Doria, Rodrigo Trevisoli ^a   Cerdeira, Antonio ^b   Raskin, Jean Pierre ^c   Flandre, Denis ^c   Pavanello, Marcelo Antonio ^a,d  

^a CENTRO UNIVERSITÁRIO DA FEI   (Brazil)

^b DEPARTAMENTO DE FÍSICA   (Mexico)

^c UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

^d UNIVERSITY OF SÃO PAULO   (Brazil)

Author keywords

Asymmetric MOSFET; Channel engineering; Double gate; Gate all around; Graded channel; Harmonic distortion; Non linearity; Silicon on insulator

Indexed keywords

DATA STORAGE EQUIPMENT; GALLIUM ALLOYS; HARMONIC ANALYSIS; HARMONIC DISTORTION; LINEARIZATION; SEMICONDUCTING SILICON COMPOUNDS; SILICON;

ASYMMETRIC MOSFET; CHANNEL ENGINEERING; DOUBLE GATE; GATE-ALL-AROUND; GRADED-CHANNEL; NON-LINEARITY; SILICON-ON-INSULATOR;

MOSFET DEVICES;

EID: 56049089662     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2008.02.006     Document Type: Article

References (24)

1. Flandre D., Colinge J.P., Chen J., De Ceuster D., Eggermont J.P., Ferreira L., Gentinne B., Jespers P.G.A., Viviani A., Gillon R., Raskin J.P., Vander Vorst A., Vanhoenacker-Janvier D., and Silveira F. Fully-depleted SOI CMOS technology for low-voltage low-power mixed digital/analog/microwave circuits. Analog Integrated Circuits Signal Process. 21 (1999) 213-228
2. Flandre D., Ferreira L.F., Jespers P.G.A., and Colinge J.P. Modeling and application of fully depleted SOI MOSFETs for low voltage, low power analogue CMOS circuits. Solid-State Electron. 39 4 (1996) 455-460
3. Colinge J.P. Silicon-on-Insulator Technology: Materials to VLSI (1991), Kluwer Academic Publishers, Dordrecht
4. Kranti A., Chung T.M., Flandre D., and Raskin J.P. Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications. Solid-State Electron. 48 6 (2004) 947-959
5. 2 and SiON gate dielectrics and TaN gate electrode. Microelectron. Eng. 80 (2005) 386-389
6. Raskin J.P., Chung T.M., Kilchytska V., Lederer D., and Flandre D. Analog/RF performance of multiple gate SOI devices: wideband simulations and characterization. IEEE Trans. Electron Devices 53 5 (2006) 1088-1095
7. Pavanello M.A., Martino J.A., and Flandre D. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects. Solid-State Electron. 44 6 (2000) 917-922
8. R.T. Doria, M.A. Pavanello, A. Cerdeira, J.P. Raskin, D. Flandre, Channel length reduction influence on harmonic distortion of graded-channel gate-all-around devices, in: 21st Symposium on Microelectronics Technology and Devices, 2006, pp. 247-256.
9. Pavanello M.A., Martino J.A., Raskin J.-P., and Flandre D. High performance analog operation of double-gate transistors with graded-channel architecture at low temperatures. Solid-State Electron. 49 10 (2005) 1569-1575
10. Cerdeira A., Alemán M.A., Pavanello M.A., Martino J.A., Vancaillie L., and Flandre D. Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor. IEEE Trans. Electron Devices 52 5 (2005) 967-972
11. Pavanello M.A., Martino J.A., and Flandre D. Analog circuit design using graded-channel SOI nMOSFETs. Solid-State Electron. 46 8 (2002) 1215-1225
12. Gimenez S.P., Pavanello M.A., Martino J.A., and Flandre D. Gain improvement in operational transconductance amplifiers using graded-channel SOI nMOSFETs. Microelectron. J. 37 1 (2006) 31-37
13. Cerdeira A., Estrada M., Quintero R., Flandre D., Ortiz-Conde A., and García Sánchez F.J. New method for determination of harmonic distortion in SOI FD transistors. Solid-State Electron. 46 1 (2002) 103-108
14. Cerdeira A., Alemán M.A., Estrada M., and Flandre D. Integral function method for determination of nonlinear harmonic distortion. Solid-State Electron. 48 12 (2004) 2225-2234
15. Kilchytska V., Neve A., Vancaillie L., Levacq D., Adriaensen S., van Meer H., De Meyer K., Raynaud C., Dehan M., Raskin J.P., and Flandre D. Influence of device engineering on the analog and RF performances of SOI MOSFETs. IEEE Trans. Electron Devices 50 3 (2003) 577-588
16. Vandooren A., Colinge J.P., and Flandre D. Gate-all-around OTA's for red-hard and high-temperature analog applications. IEEE Trans. Nucl. Sci. 46 4 (1999) 1242-1249
17. Athena Users' Manual, Edition 10, 2004.
18. Atlas Users Manual, 2004.
19. Pavanello M.A., Martino J.A., and Flandre D. Analog performance and applications of graded-channel fully depleted SOI MOSFETs. Solid-State Electron. 44 7 (2000) 1219-1222
20. Sakurai S., and Ismail M. Low-voltage CMOS Operational Amplifiers Theory, Design and Implementation (1994), Kluwer Academic Publishers, Dordrecht
21. Wanbacq P., and Sansen W. Distortion Analysis of Integrated Circuits (1998), Kluwer Academic Publishers, Dordrecht
22. de Souza M., Pavanello M.A., Iñiguez B., and Flandre D. A charge-based continuous model for submicron graded-channel nMOSFET for analog circuit simulation. Solid-State Electron. 49 10 (2005) 1683-1692
23. M.A. Pavanello, A. Cerdeira, J.A. Martino, J.P. Raskin, D. Flandre, Impact of asymmetric channel configuration on the linearity of double-gate SOI MOSFETs, in: Proceedings of the 6th ICCDCS, 2006, pp. 187-191.
24. A. Cerdeira, M. Alemán, V. Kilchitska, N. Collaert, K. De Meyer, D. Flandre, Nonlinearity analysis of FinFETs, in: Proceedings of the 6th ICCDCS, 2006, pp. 9-12.