Fabrication cost analysis and cost-aware design space exploration for 3-D ICs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 29, Issue 12, 2010, Pages 1959-1972

  Dong, Xiangyu ^a   Zhao, Jishen ^a   Xie, Yuan ^a  

^a The Pennsylvania State University   (United States)

Author keywords

3 D integration; application specific integrated circuit (ASIC); cost; microprocessor

Indexed keywords

3-D ICS; 3-D INTEGRATED CIRCUIT; 3-D INTEGRATION; APPLICATION-SPECIFIC INTEGRATED CIRCUIT (ASIC); COST ANALYSIS; COST BENEFITS; COST ESTIMATION METHODS; COST EVALUATIONS; COST MODELS; DESIGN SPACE EXPLORATION; DESIGN STRATEGIES; EARLY DESIGN STAGES; FABRICATION COST; HETEROGENEOUS INTEGRATION; IC DESIGNS; MANY-CORE; MICROPROCESSOR; MICROPROCESSOR DESIGNS; PARTITIONING STRATEGIES; SYSTEM LEVELS; TRANSISTOR COUNT;

COST ACCOUNTING; COSTS; DESIGN; ELECTRIC POWER SUPPLIES TO APPARATUS; ESTIMATION; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; INTEGRATION; MICROPROCESSOR CHIPS; SPACE RESEARCH; THREE DIMENSIONAL; WAFER BONDING;

COST BENEFIT ANALYSIS;

EID: 78649372034     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2010.2062811     Document Type: Article

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