Mitigating ISI through self-calibrating continuous-time equalization

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 53, Issue 10, 2006, Pages 2234-2245

  Hollis, Timothy M ^a   Comer, David J ^a   Comer, Donald T ^a  

^a BRIGHAM YOUNG UNIVERSITY   (United States)

Author keywords

Adaptive filters; Channel equalization; Continuous time filters; Intersymbol interference (ISI)

Indexed keywords

ADAPTIVE FILTERING; CALIBRATION; COMPUTER SIMULATION; INTERSYMBOL INTERFERENCE; OPTIMIZATION; TIMING CIRCUITS;

CHANNEL EQUALIZATION; CONTINUOUS-TIME FILTERS; SELF-CALIBRATING CONTINUOUS-TIME EQUALIZATION;

EQUALIZERS;

EID: 33750413365     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2006.883168     Document Type: Article

References (23)

1. R. W. Lucky, L. N. Holzman, F. K. Becker, and E. Port, "Automatic equalization for digital communication," in Proc. IEEE, Jan. 1965, vol. 53, no. 1, pp. 96-97.
2. R. W. Lucky and H. R. Rudin, "Generalized automatic equalization for communication channels," in Proc. IEEE, Mar. 1966, vol. 53, no. 3, pp. 439-440.
3. S. Reynolds, P. Pepeljugoski, J. Schaub, J. Tierno, and D. Beisser, "A 7-tap transverse analog-FIR filter in 0.13 μm CMOS for equalization of 10-Gb/s fiber-optic data systems," in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2005, pp. 330-331.
4. M. E. Said, J. Sitch, and M. Elmasry, "A 0.5-μm SiGe pre-equalizer for 10-Gb/s single-mode fiber optic links," in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2005, pp. 224-225.
5. M. E. Austin, Decision-feedback equalization for digital communication over dispersive channels Massachusetts Institute of Technology: Research Laboraory of Electronics, Cambridge, 1967, Tech. Rep. 461.
6. M. Sorna, T. Beukema, K. Selander, S. Zier, B. Ji, P. Murfet, J. Mason, W. Rhee, H. Ainspan, and B. Parker, "A 6.4-Gb/s CMOS SerDes core with feedforward and decision-feedback equalization," in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2005, pp. 62-63.
7. R. Payne, B. Bhakta, S. Ramaswamy, S. Wu, J. Powers, P. Landman, U. Erdogan, A. Yee, R. Gu, L. Wu, Y. Xie, B. Parthasarathy, K. Brouse, W. Mohammed, K. Heragu, V. Gupta, L. Dyson, and W. Lee, "A6.25-Gb/s binary adaptive DFE with first post-cursor tap cancellation for serial backplane communications," in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2005, pp. 68-69.
8. J. W. M. Bergmans, "Digital magnetic recording systems," IEEE Trans. Magn., vol. 24, pt. 1, pp. 683-688, Jan. 1988.
9. J. E. C. Brown, P. J. Hurst, B. C. Rothenberg, and S. H. Lewis, "A CMOS adaptive continuous-time forward equalizer, LPF, and RAM-DFE for magnetic recording," IEEE J. Solid-State Circuits, vol. 34, no. 2, pp. 162-169, Feb. 1999.
10. R. S. Kajley, J. E. C. Brown, and P. J. Hurst, "A mixed-signal decision-feedback equalizer that uses a look-ahead architecture," IEEE J. Solid-State Circuits, vol. 32, no. 3, pp. 450-459, Mar. 1997.
11. J. E. Jaussi, G. Balamurugan, D. R. Johnson, B. K. Casper, A. Martin, J. Kennedy, N. Shanbhag, and R. Mooney, "8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 80-88, Jan. 2005.
12. Y. Tomita, M. Kibune, J. Ogawa, W. W. Walker, H. Tamura, and T. Kuroda, "A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS," IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 986-993, Apr. 2005.
13. H. Higashi, S. Masaki, M. Kibune, S. Matsubara, T. Chiba, Y. Doi, H. Yamaguchi, H. Ishida, K. Gotoh, and H. Tamura, "A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization," IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 978-985, Apr. 2005.
14. E. A. Vittoz, Micropower Techniques. Englewood Cliffs, NJ: Prentice-Hall, 1994.
15. D. M. Binkley, C. E. Hopper, S. D. Tucker, B. C.Moss, J. M. Rochelle, and D. P. Foty, "A cad methodology for optimizing transistor current and sizing in analog CMOS design," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 2, pp. 225-237, Feb. 2003.
16. D. J. Comer and D. T. Comer, "Operation of analog MOS circuits in the weak or moderate inversion region," IEEE Trans. Educ., vol. 47, no. 5, pp. 430-435, Nov. 2004.
17. D. J. Comer and D. T. Comer, "Using the weak inversion region to optimize input stage design of op amps," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 51, no. 1, pp. 8-14, Jan. 2004.
18. T. M. Hollis, D. J. Comer, and D. T. Comer, "Optimization of MOS amplifier performance through channel length and inversion level selection," IEEE Trans. Circuits Syst. II, Expr. Briefs, vol. 52, no. 9, pp. 545-549, Sep. 2005.
19. J. M. Mendel, "Tutorial on higher-order statistics (spectra) in signal processing and system theory: Theoretical results and some applications," Proc. IEEE, vol. 79, pp. 278-305, Mar. 1991.
20. R. P. Sallen and E. L. Key, "A practical method for designing RC active filters," IRE Trans. Circuit Theory, vol. CT-2, pp. 74-85, Mar. 1955.
21. D. J. Comer and J. E. McDermid, "Inductorless bandpass characteristics using all-pass networks," IEEE Trans. Circuit Theory, vol. CT-17, no. 12, pp. 501-503, Dec. 1968.
22. Y. Chang, J. Choma, and J. Wills, "The design of CMOS gigahertzband continuous-time active low-pass filters with Q-enhancement circuits," in Proc. 9th Great Lakes Symp. VLSI, Mar. 1999, pp. 358-361.
23. T. M. Hollis, D. J. Comer, and D. T. Comer, "Self-calibrating continuous-time equalization targeting inter-symbol interference," in Proc. IEEE Northeast Workshop Circuits Syst., Jun. 2006.