Deposited thin SiO2 for gate oxide on n-type and p-type GaN

Journal of the Electrochemical Society

Volumn 157, Issue 11, 2010, Pages

  Placidi, M ^a   Constant, A ^a   Fontser A ^a   Pausas, E ^a   Cortes, I ^a   Cordier, Y ^c   Mestres, N ^b   Prez R ^d   Zabala, M ^a   Millan J ^a   Godignon, P ^a   Prez Tomas A ^a  

^a INSTITUTO DE MICROELECTRÓNICA DE BARCELONA   (Spain)

^b UNIVERSITAT AUTÒNOMA DE BARCELONA   (Spain)

^c CRHEA CNRS   (France)

^d UNIVERSITY OF BARCELONA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; ATOMIC FORCE MICROSCOPY; CAPACITANCE; GALLIUM NITRIDE; GATES (TRANSISTOR); III-V SEMICONDUCTORS; INTERFACE STATES; PLASMA CVD; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; SCANNING ELECTRON MICROSCOPY; SECONDARY ION MASS SPECTROMETRY; SURFACE ROUGHNESS;

C-V MEASUREMENT; CAPACITANCE VOLTAGE; CURRENT VOLTAGE; DIFFUSION MECHANISMS; ELECTRICAL CHARACTERISTIC; INTERFACE STATE DENSITY; INTERFACIAL TRAP DENSITIES; TETRA-ETHYL-ORTHO-SILICATE;

SILICA;

EID: 77957706655     PISSN: 00134651     EISSN: None     Source Type: Journal    
DOI: 10.1149/1.3486091     Document Type: Article

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