A fault-tolerant interconnect mechanism for NMR nanoarchitectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 10, 2010, Pages 1433-1446

  Namazi, Ali ^a   Nourani, Mehrdad ^b,c   Saquib, Mohammad ^c  

^a INTELLIGENT AUTOMATION INC   (United States)

^b UNIVERSITY OF TEXAS AT DALLAS   (United States)

^c The University of Texas at Dallas   (United States)

Author keywords

Code division multiple access (CDMA); communication grid; fault tolerance; N tuple modular redundancy (NMR); nanometer VLSI; on chip interconnect; triple module redundancy (TMR); voter

Indexed keywords

COMMUNICATION GRID; MODULAR REDUNDANCY; NANOMETER VLSI; ON CHIP INTERCONNECT; TRIPLE MODULE REDUNDANCY; VOTER;

CODE DIVISION MULTIPLE ACCESS; DATA TRANSFER RATES; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; INTERCONNECTION NETWORKS; NANOSYSTEMS; QUALITY ASSURANCE;

REDUNDANCY;

EID: 77957561742     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2024779     Document Type: Article

References (42)

1. M. Breuer, S. Gupta, and T. Mak, "Defect and error tolerance in the presence of massive numbers of defects," IEEE Des. Test Comput., vol.21, no.3, pp. 216-227, May/Jun. 2004.
2. P. Yu, S. Shi, and D. Pan, "Process variation aware OPC with variational lithography modeling," in Proc. 43rd ACM/IEEE Des. Autom. Conf., Jul. 2006, pp. 785-790.
3. A. Agarwal, K. Kang, and K. Roy, "Accurate estimation and modeling of total chip leakage considering inter and intra-die process variations," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des. (ICCAD), Nov. 2005, pp. 736-741.
4. S. Borkar, "Designing reliable systems from unreliable components: The challenges of transistor variability and degradation," IEEE Micro, vol.25, no.6, pp. 10-16, Nov. 2005.
5. J. Appenzeller, J. Knoch, R. Martel, V. Derycke, S. Wind, and P. Avouris, "Carbon nanotube electronics," IEEE Trans. Nanotechnol., vol.1, no.4, pp. 184-189, Dec. 2002.
6. C. Lent and P. Tougaw, "A device architecture for computing with quantum dots," Proc. IEEE, vol.85, no.4, pp. 541-557, Apr. 1997.
7. K. Likharev, "Single-electron devices and their applications," Proc. IEEE, vol.87, no.4, pp. 606-632, Apr. 1999.
8. T. Raja, V. Agrawal, and M. Bushnell, "A tutorial on the emerging nanotechnology devices," in Proc. 17th Int. Conf. VLSI Des., 2004, pp. 343-360.
9. Semiconductor Industry Association, "The International Technology Roadmap for Semiconductors: 2005 Update," 2005. [Online]. Available: Available: http://www.itrs.net/Links/2005ITRS/ERD2005.pdf
10. S. Borkar, "Microarchitecture and design challenges for gigascale integration," in Keynote Speech Micro 2004 Conf., Dec. 2004, p. 3. (Pubitemid 40927681)
11. S. Mitra and E. McCluskey, "Word-voter: A new voter design for triple modular redundant systems," in Proc. IEEE VLSI Test Symp., May 2000, pp. 465-470.
12. J. von Neumann, "Probabilistic logics and the synthesis of reliable organisms from unreliable components," in Automata Studies, C. E. Shannon and J. McCarthy, Eds. Princeton, NJ: Princeton Univ. Press, 1956, pp. 43-98.
13. P. Yang and J. Chern, "Design for reliability: The major challenge for VLSI," Proc. IEEE, vol.81, no.5, pp. 730-744, May 1993.
14. J. Sklaroff, "Redundancy management technique for space shuttle computers," IBM J. Res. Dev., vol.20, no.1, pp. 20-28, Jan. 1976.
15. P. Hansen, M. Linton, R. Mayo, M. Murphy, and D. Patterson, "Introduction to the iAPX 482 architecture," ACM SIGARCH Comput. Arch. News, vol.10, no.4, pp. 17-26, 1982.
16. W. Peterson and E. Weldon, Error-Correcting Codes, 2nd ed. Cambridge, MA: MIT Press, 1972.
17. A. Agarwal, B. Paul, S. Mukhopadhyay, and K. Roy, "Process variation in embedded memories: Failure analysis and variation aware architecture," IEEE J. Solid-State Circuits, vol.40, no.9, pp. 1804-1814, Sep. 2005.
18. S. Roy and V. Beiu, "Majority multiplexing-economical redundant fault-tolerant designs for nanoarchitectures," IEEE Trans. Nanotechnol., vol.4, no.4, pp. 441-451, Jul. 2005.
19. J. Han, J. Gao, P. Jonker, Y. Qi, and J. A. B. Fortes, "Toward hardware- redundant, fault-tolerant logic for nanoelectronics," IEEE Des. Test Comput., vol.22, no.4, pp. 328-339, Jul./Aug. 2005.
20. C. He, M. Jacome, and G. Veciana, "A reconfiguration-based defect- tolerant design paradigm for nanotechnologies," IEEE Des. Test Comput., vol.22, no.4, pp. 316-326, Jul./Aug. 2005.
21. M. Stan, P. Franzon, S. Goldstein, J. Lach, and M. Ziegler, "Molecular electronics: From devices and interconnect to circuits and architecture," Proc. IEEE, vol.91, no.11, pp. 1940-1957, Nov. 2003.
22. A. DeHon, "Array-based architecture for FET-based, nanoscale electronics," IEEE Trans. Nanotechnol., vol.2, no.1, pp. 23-32, Mar. 2003.
23. K. Granhaug and S. Aunet, "Improving yield and defect tolerance in subthreshold CMOS through output-wired redundancy," J. Electron. Testing, vol.24, no.1-3, pp. 157-163, Jun. 2008.
24. S. Tam, S. Rusu, U. Desai, R. Kim, J. Zhang, and I. Young, "Clock generation and distribution for the first IA-64 microprocessor," IEEE J. Solid-State Circuits, vol.35, no.11, pp. 1545-1552, Nov. 2000. (Pubitemid 32070546)
25. P. McEuen, M. Fuhrer, and H. Park, "Single-walled carbon nanotube electronics," IEEE Trans. Nanotechnol., vol.1, no.1, pp. 78-85, Mar. 2002.
26. A. Ganguly, P. Pande, and B. Belzer, "Crosstalk-aware channel coding schemes for energy efficient and reliable NOC interconnects," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., to be published.
27. J. Proakis, Digital Communications, 4th ed. New York: McGraw- Hill, Aug. 2000.
28. W. Chung and D. Ha, "A new approach for massive parallel scan design," presented at the Proc. Int. Test Conf., Austin, TX, 2005.
29. X. Wang and J. Nurmi, "Exploration of CDMA-based network-onchip," presented at the Workshop Future Interconnects Netw. Chip, Munich, Germany, Mar. 2006.
30. M. Kim, D. Kim, and G. Sobelman, "Design of a high-performance scalable CDMA router for on-chip switched networks," in Proc. Int. SoC Des. Conf., 2005, pp. 32-35.
31. A. Namazi, M. Nourani, and M. Saquib, "A robust interconnect mechanism for nanometer VLSI," presented at the Int. Test SynthesisWorkshop (ITSW), San Antonio, TX, Mar. 2007.
32. A. Namazi and M. Nourani, "Distributed voting for fault-tolerant nanoscale systems," in Proc. IEEE Int. Conf. Comput. Des. (ICCD), Oct. 2007, pp. 568-573.
33. P. Gray, P. Hurst, S. Lewis, and R. Meyer, Analysis and Design of Analog Integrated Circuit. New York: Wiley, 2000.
34. J. M. Musicer and J. Rabaey, "MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments," in Proc. Int. Symp. Low Power Electron. Des. (ISLPED), 2000, pp. 102-107.
35. S. Bruma, "Impact of on-chip process variations on MCML performance," in Proc. IEEE Int. SOC Conf., Sep. 2003, vol.16, no.3, pp. 135-140.
36. T. Cover and J. Thomas, Elements of Information Theory. New York: Wiley, 1991.
37. B. Parhami, "Voting networks," IEEE Trans. Rel., vol.40, no.3, pp. 380-394, Aug. 1991.
38. Synopsys, Inc., Mountain View, CA, "User Manuals for Synopsys Tools v2005.06," 2005.
39. The MathWorks, Inc., Natick, MA, "User Manuals for Matlab 7.0 Toolset," 2005.
40. Nanoscale Integration and Modeling (NIMO) Group, Arizona State Univ., Tempe, AZ, "Predictive technology model," [Online].Available: http://www.eas.asu.edu/~ptm/
41. Cadence Design Systems, Inc., San Jose, MA, "Cadence design toolset v5.0.0," 2005.
42. IBM, Inc., "130 nm spice models," 2005.