A reconfiguration-based defect-tolerant design paradigm for nanotechnologies

IEEE Design and Test of Computers

Volumn 22, Issue 4, 2005, Pages 316-326

  He, Chen ^a,b   Jacome, Margarida F ^a   de Veciana, Gustavo ^a  

^a The University of Texas at Austin   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; FAST FOURIER TRANSFORMS; FAULT TOLERANT COMPUTER SYSTEMS; LOGIC DEVICES; PROBABILITY; TABLE LOOKUP;

DEFECT TOLERANT DESIGN; LOGIC CONTROL;

NANOTECHNOLOGY;

EID: 24344474864     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2005.76     Document Type: Article

References (12)

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